John L Rapp

US Patent:

7768523, Aug 3, 2010

Filed:

Mar 9, 2006

Appl. No.:

11/373755

Inventors:

Daniel K. Baker - Bellevue WA, US
Michael V. Oneppo - Kirkland WA, US
Samuel Glassenberg - Kirkland WA, US
John Rapp - Seattle WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G09G 5/00

US Classification:

345582, 345426, 345427, 345587, 345608, 345609, 345610

Abstract:

In a technique for rendering non-linear BRDFs that are stable in both the temporal and spatial domains, without serious interruption to the content creation pipeline used in most games, non-linear content is linearized by rendering in texture space at a fixed resolution. A MIP-map chain is calculated from this texture. The complete MIP-map chain is used for rendering on a display device. Low resolution reflectance parameters are used to approximate the highest resolution reflectance parameters as the object becomes smaller on the display device. The low resolution reflectance parameters are calculated using non linear fitting techniques.

US Patent:

7973799, Jul 5, 2011

Filed:

Jul 2, 2010

Appl. No.:

12/829896

Inventors:

Daniel K. Baker - Bellevue WA, US
Michael V. Oneppo - Kirkland WA, US
Samuel Glassenberg - Kirkland WA, US
John Rapp - Seattle WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G09G 5/00

US Classification:

345587, 345426, 345582, 345584, 345644

Abstract:

In a technique for rendering non-linear BRDFs that are stable in both the temporal and spatial domains, without serious interruption to the content creation pipeline used in most games, non-linear content is linearized by rendering in texture space at a fixed resolution. A MIP-map chain is calculated from this texture. The complete MIP-map chain is used for rendering on a display device. Low resolution reflectance parameters are used to approximate the highest resolution reflectance parameters as the object becomes smaller on the display device. The low resolution reflectance parameters are calculated using non linear fitting techniques.

US Patent:

8432398, Apr 30, 2013

Filed:

Nov 5, 2009

Appl. No.:

12/613371

Inventors:

John Rapp - Seattle WA, US
Andrew Bliss - Kirkland WA, US
Shai Hinitz - Redmond WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06T 11/20

US Classification:

345440, 345581, 345619, 717104, 717105, 717114, 717124, 717125, 717127, 717131, 717144

Abstract:

Systems, methods, and computer storage media having computer-executable instructions embodied thereon determine whether an output value of a dependency graph has a particular characteristic. In one embodiment, to make this determination, a dependency graph is generated that illustrates external and internal nodes, in addition to their dependency to one another. External nodes, or those nodes that do not depend on other nodes, are analyzed to determine whether they have a particular characteristic. Depending on the operation associated with the characteristic, it may then be determined whether the output value of the dependency graph also has that characteristic.

US Patent:

8510724, Aug 13, 2013

Filed:

Dec 17, 2010

Appl. No.:

12/972198

Inventors:

Yosseff Levanoni - Redmond WA, US
Weirong Zhu - Issaquah WA, US
Lingli Zhang - Sammamish WA, US
John Lee Rapp - Redmond WA, US
Andrew L. Bliss - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/45

US Classification:

717136, 717137, 717140, 717145, 717146

Abstract:

The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into High Level Shader Language (“HLSL”) source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.

US Patent:

8581912, Nov 12, 2013

Filed:

Jun 27, 2008

Appl. No.:

12/163734

Inventors:

Michael V. Oneppo - Seattle WA, US
Craig Peeper - Bellevue WA, US
Andrew L. Bliss - Kirkland WA, US
John L. Rapp - Seattle WA, US
Mark M. Lacey - Seattle WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 15/00
G06T 15/50

US Classification:

345501, 345426

Abstract:

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.

US Patent:

8635501, Jan 21, 2014

Filed:

Jul 25, 2011

Appl. No.:

13/190074

Inventors:

John Lee Rapp - San Diego CA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 11/00

US Classification:

714 48

Abstract:

A computer-implemented method, computer-readable media, and a computerized system to track and detect data hazards are provided. The computerized system includes processors configured to execute instructions associated with a multithreaded program. The computerized system allocates memory for the multithreaded program and creates threads for execution on the processors. The memory may include a reserved area for tracking information. The threads access the allocated memory in accordance with the multithreaded program and the memory including the tracking information is updated based on the threads' memory access. In turn, the processors generate notifications of data hazard based on the tracking information stored in the allocated memory.

US Patent:

20120159258, Jun 21, 2012

Filed:

Dec 15, 2010

Appl. No.:

12/969482

Inventors:

Paul E. Maybee - Seattle WA, US
Eric S. Leese - Seattle WA, US
John Lee Rapp - Redmond WA, US
Maria K. Blees - Seattle WA, US

Assignee:

MICROSOFT CORPORATION - Redmond WA

International Classification:

G06F 11/36

US Classification:

714 381, 714E1121

Abstract:

The debugging of a program in a data parallel environment. A connection is established between a debugging module and a process of the data parallel environment. The connection causes the data parallel environment to notify the debugging module of certain events as they occur in the execution of the process. Upon notification of such an event, the process execution is paused, and the debugging module may query the data parallel environment for information regarding the process at the device independent virtual machine layer. Upon completion of this querying, the process may then resume execution. This may occur repeatedly if multiple events are encountered.

US Patent:

20120167062, Jun 28, 2012

Filed:

Dec 27, 2010

Appl. No.:

12/979094

Inventors:

Yosseff Levanoni - Redmond WA, US
Weirong Zhu - Issaquah WA, US
Lingli Zhang - Sammamish WA, US
John Lee Rapp - Redmond WA, US
Andrew L. Bliss - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 9/45

US Classification:

717138, 717136, 717146

Abstract:

The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.