John T Rawlins

US Patent:

6400257, Jun 4, 2002

Filed:

Jul 26, 2000

Appl. No.:

09/625885

Inventors:

Yuen H. Chan - Poughkeepsie NY
Anuj Kohli - Maple Grove MN
John R. Rawlins - New Paltz NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05B 100

US Classification:

3401462, 326 52

Abstract:

A high performance CMOS comparator circuit is integrated with a bypass function allowing comparing first and second data sets (A B) with a high data width (more than 30 and illustrated as 48 bits). In many cases, it is often required to compare not only sets AB but also set A with an additional bypass set, and the preferred circuit embodiment permits this to be achieved.

US Patent:

6788112, Sep 7, 2004

Filed:

May 12, 2003

Appl. No.:

10/436229

Inventors:

Yuen H. Chan - Poughkeepsie NY
Rajiv Joshi - Yorktown Heights NY
Antonio R. Pelella - Highland Falls NY
John R. Rawlins - New Paltz NY
Jatinder K. Wadhwa - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 1900

US Classification:

327 51, 327 55, 327 57, 36518905, 36523009

Abstract:

A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.

US Patent:

6958943, Oct 25, 2005

Filed:

May 12, 2004

Appl. No.:

10/844301

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Timothy J. Charest - West Hurley NY, US
John R. Rawlins - New Paltz NY, US
Arthur D. Tuminaro - Lagrangeville NY, US
Jatinder K. Wadhwa - Wappingers Falls NY, US
Otto M. Wagner - Altdorf, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C007/00

US Classification:

365194, 365205, 365233

Abstract:

A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

US Patent:

7054184, May 30, 2006

Filed:

May 12, 2004

Appl. No.:

10/844296

Inventors:

Yuen H. Chan - Poughkeepsie NY, US
Timothy J. Charest - West Hurley NY, US
Antonio R. Pelella - Highland Falls NY, US
John R. Rawlins - New Paltz NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 11/00
G11C 7/00

US Classification:

365154, 365156, 36518908

Abstract:

A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.

US Patent:

54040493, Apr 4, 1995

Filed:

Nov 2, 1993

Appl. No.:

8/146253

Inventors:

Miles G. Canada - Colchester VT
Michael Nicewicz - Jericho VT
John R. Rawlins - Wallkill NY
Carlos G. Rivadeneira - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 720

US Classification:

327525

Abstract:

A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse latch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.

US Patent:

53134303, May 17, 1994

Filed:

Dec 9, 1992

Appl. No.:

7/987923

Inventors:

John R. Rawlins - Wallkill NY
Carlos G. Rivadeneira - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1140

US Classification:

365229

Abstract:

A power down circuit for a default detection circuit, for detecting defects in memory array cells, comprising means for diverting the memory array standby current around the memory array cells to achieve the maximum ratio of change in input voltage as compared to the change in cell standby current and to provide improved tracking of the memory array over statistical variations of temperature, power supplies, process and other variables.