John D Repp

US Patent:

6924713, Aug 2, 2005

Filed:

Oct 15, 2002

Appl. No.:

10/270115

Inventors:

John Donald Repp - Doylestown PA, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H01P005/00
H01P001/15

US Classification:

333 24R, 333103, 333177

Abstract:

Many current electronic systems incorporate expensive or sensitive electrical components. Because electrical energy is often generated or transmitted at high voltages, the power supplies to these electronic systems must be carefully designed. Power supply design must ensure that the electrical system being supplied with power is not exposed to excessive voltages or currents. In order to isolate power supplies from electrical equipment, many methods have been employed. These methods typically involve control systems or signal transfer methods. However, these methods are not always suitable because of their drawbacks. The present invention relates to transmitting information across an interface. More specifically, the present invention provides an apparatus for transmitting both AC and DC information across a high bandwidth magnetic interface with low distortion.

US Patent:

49165763, Apr 10, 1990

Filed:

Feb 27, 1989

Appl. No.:

7/316091

Inventors:

Edward Herbert - Canton CT
John D. Repp - Barkhamsted CT

Assignee:

FMTT, Inc. - Canton CT

International Classification:

H05K 700
H01R 1366

US Classification:

361393

Abstract:

A multipin matrix capacitor includes a first and second electrode separated by a dielectric material to form a capacitive element and includes terminals for connecting it to the first and second electrode wherein the terminals are distributed along the electrodes in a grid arrangement. Inductances are minimized or substantially eliminated in lead connections to the matrix capacitor due to the reduced conduction path lengths possible between an external component and the capacitor since access to the capacitor is provided at substantially all areas of the electrodes forming the capacitor. In one aspect of the invention, DC current is conducted along the surface of conductive sheets comprising the electrodes.

US Patent:

49423533, Jul 17, 1990

Filed:

Sep 29, 1989

Appl. No.:

7/415043

Inventors:

Edward Herbert - Canton CT
John D. Repp - Barkhamsted CT
Stephen E. Cebry - Burlington CT

Assignee:

FMTT, Inc. - Canton CT

International Classification:

H01F 3300

US Classification:

323361

Abstract:

A high frequency matrix transformer power converter module includes a dedicated, pre-wired secondary winding, inductor and filter capacitor wherein the electrical conductor forming the dedicated secondary winding is made from a flat ribbon material and passes through adjacent cores forming the interdependent magnetic elements of the matrix transformer such that helical portions of the conductor forming the winding are in complementary arrangement within the core structure and provide an opening through which a second electrical conductor forming a primary winding may be inserted after the module is constructed to obtain the desired transformation characteristics. A number of modules may be arranged side-by-side to provide a higher power output wherein the output voltage busses of the modules are connected together and wherein through holes of each module are in registry to permit wiring of an undedicated primary winding to obtain the desired power output.

US Patent:

47884622, Nov 29, 1988

Filed:

Feb 12, 1987

Appl. No.:

7/013757

Inventors:

Richard V. Vesce - East Hampton CT
John D. Repp - Canton CT

Assignee:

United Technologies Corporation - Hartford CT

International Classification:

H03K 5153
H03K 1722

US Classification:

307597

Abstract:

A Power-On-Reset (POR) Circuit compares a logic supply voltage to a reference voltage and provides a logic voltage validity signal if the logic voltage is greater than the reference voltage; the circuit delays, on startup, the validity signal for a selected period and then provides a drive signal for driving a solid-state switch which provides an open circuit on the presence of the drive signal, indicating logic voltage validity, and a short circuit in its absence, indicating invalidity; and the circuit immediately disables the drive signal if the logic voltage falls below the reference voltage. The selected start-up delay period is independent of the supply voltage magnitude.