John R Richards

US Patent:

6349079, Feb 19, 2002

Filed:

Oct 8, 1999

Appl. No.:

09/414745

Inventors:

Karl A. Belser - San Jose CA
Lawrence M. Bryant - Palo Alto CA
John H. Richards - San Jose CA

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G11B 700

US Classification:

369 4426, 369 4434, 369 5328

Abstract:

A system and method are provided for processing signals in a magneto-optical computer memory device to detect mispositioning of a head with respect to a track centerline. A light beam is scanned over a first and a second set of radially offset optically-detectable position marks formed in the rotating medium surface. A detector receives the reflected light beam and responsively generates a position signal having a plurality of pulses corresponding to the position marks. The position signal is then passed through a differentiator circuit. The differentiated position signal may then be applied to low pass filter and resonator circuits, and is subsequently conveyed to a finite time integrator for rectification and detection of the areas of the pulses associated with the first and second set of position marks. Mispositioning of the head is detected by comparing the pulse areas of the first and second set of position marks.

US Patent:

6355981, Mar 12, 2002

Filed:

Jan 21, 1999

Appl. No.:

09/235135

Inventors:

John G. Richards - San Jose CA
Wendell B. Sander - Los Gatos CA

Assignee:

ChipScale, Inc. - San Jose CA

International Classification:

H01L 2348

US Classification:

257735, 257725, 257730, 257728, 257693, 257702, 257773, 257724, 257734

Abstract:

A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom. Sawing forms the outside surface of the post and completes the finished device without subsequent assembly.

US Patent:

54418984, Aug 15, 1995

Filed:

Dec 29, 1994

Appl. No.:

8/363732

Inventors:

John G. Richards - San Jose CA
Hector Flores - San Jose CA
Wendell B. Sander - Los Gatos CA

Assignee:

Micro Technology Partners - San Jose CA

International Classification:

H01L 2900

US Classification:

437 15

Abstract:

An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure. A substantially planar first metallic pad is provided for a first connection to external circuitry.

US Patent:

59044969, May 18, 1999

Filed:

Jan 24, 1997

Appl. No.:

8/788764

Inventors:

John G. Richards - San Jose CA
Donald P. Richmond - Palo Alto CA
Wendell B. Sander - Los Gatos CA

Assignee:

Chipscale, Inc. - San Jose CA

International Classification:

H01L21/44;21/48;21/50

US Classification:

438106

Abstract:

A packaging technique for electronic devices includes wafer fabrication of contacts that wrap down the inside surface of a substrate post. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. A trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold beam wire extends from a connection point within the circuit into the trench. Unless an insulative substrate is used, the wire runs over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back planed to form the bottom surface of the post. Then it is selectively back etched, to expose the bottom surface of the wire, to form the inside surface of the post, and to form the bottom surface of the finished device. A solderable lead wire runs from the exposed gold wire, down the inside surface of the post, and across its bottom.

US Patent:

6232067, May 15, 2001

Filed:

Aug 17, 1998

Appl. No.:

9/135381

Inventors:

Michael W. Hunkapiller - San Carlos CA
John H. Richards - Bradbury CA

Assignee:

The Perkin-Elmer Corporation - Foster City CA

International Classification:

C12Q 168

US Classification:

435 6

Abstract:

The present invention relate to methods and compositions for simultaneously analyzing multiple different polynucleotides of a polynucleotide composition comprising multiple diverse polynucleotide sequences. The subject methods and compositions may also be applied to analyze or identify single polynucleotides; however, the subject methods and compositions are particularly useful for analyzing large diverse populations of polynucleotides, e. g. , cDNA libraries. Most embodiments of the invention involve hybridizing terminus probes (of known base sequence) and internal fragment probes (of known base sequence) at adjacent positions on an adapter-modified restriction fragment generated from polynucleotide for analysis, and subsequently joining the terminus probes and internal fragment probes to each other. The terminus probe hybridizes to bases of restriction endonuclease recognition site present at the terminus of a restriction fragment generated from the polynucleotide for analysis. Internal fragment probes hybridizes to the same strand of the restriction fragment that the terminus probe hybridizes to and hybridizes to the restriction fragment portion of adapter-modified representative restriction fragments.

US Patent:

61211192, Sep 19, 2000

Filed:

May 29, 1997

Appl. No.:

8/865357

Inventors:

John G. Richards - San Jose CA
Hector Flores - San Jose CA

Assignee:

Chipscale, Inc. - San Jose CA

International Classification:

H01L 2178
H01L 21301
H01L 2146

US Classification:

438462

Abstract:

The fabrication of a resistor structure is described. A resistive region is formed over the top of a substrate. Trenches are formed from the top side of the substrate in scribe line regions where the wafer is to be separated to form resistor modules. Contact layers are formed over the top side of the substrate and are electrically coupled to each end of the resistive region, respectively. The contact layers are also formed over the sidewalls of the trenches. The wafer is separated through the trenches, creating resistor modules having sidewall contact regions.

US Patent:

53331389, Jul 26, 1994

Filed:

Mar 11, 1992

Appl. No.:

7/849740

Inventors:

John H. Richards - San Jose CA
Karl D. Schuh - San Jose CA

Assignee:

MiniStor Peripherals International Limited - San Jose CA

International Classification:

G06F 1100
G11B 1504

US Classification:

371 7

Abstract:

Apparatus for preventing data corruption on a disk due to mechanical shock occurring during the write process to the disk includes a mechanical shock sensor to sense mechanical shocks having a magnitude exceeding a predetermined threshold. Write disable circuitry responsive to the mechanical shock sensor interrupts the write current to the disk drive write head. Repositioning circuitry then repositions the data head over the original data track and the incomplete data that was interrupted by the mechanical shock is rewritten. A method for preventing data corruption on a disk due to mechanical shock experienced by a disk drive during the write process to the disk includes the steps of sensing a mechanical shock having a magnitude exceeding a predetermined threshold; storing information identifying the data being written at the onset of the sensed shock; interrupting the write current to the write head; repositioning the data head to the original track; and rewriting the data which was interrupted because of the sensed shock.

US Patent:

59124270, Jun 15, 1999

Filed:

Jan 31, 1995

Appl. No.:

8/381170

Inventors:

Kenneth Ellsworth Willis - Redwood City CA
Martin Gerald Richman - Salinas CA
William David Fahey - Cupertino CA
John Gareth Richards - San Jose CA
David S. Whang - San Jose CA

Assignee:

Quantic Industries, Inc. - San Carlos CA

International Classification:

F42B 313

US Classification:

1022028

Abstract:

This invention discloses a method of fabricating an electroexplosive device which utilizes a semiconductor bridge as an ignition element. The semiconductor bridge is electrically connected to a metal header by a small, low resistance contact to the extension of bridge material and through an insulating silicon substrate to an eutectic bond created by gold plating on the metal header and the silicon. The second electrode of the bridge circuit is connected via wire bonds to one or two conducting pins which penetrate the metal header and are insulated by surrounding glass. A redundant connection via two conducting pins insulated from the header to one electrode of the semiconductor bridge allows a post assembly test of the integrity of the wire bonds, thereby increasing reliability of the device.