John J Schuler

US Patent:

8307068, Nov 6, 2012

Filed:

Jun 17, 2009

Appl. No.:

12/486736

Inventors:

John A. Schuler - Chandler AZ, US

Assignee:

Volonics Corporation - Gilbert AZ

International Classification:

G06F 15/173
G06F 15/16
G06F 15/177
G06F 3/048

US Classification:

709224, 709223, 709225, 715867, 715736, 726 11, 726 12

Abstract:

A system for monitoring and regulating computer usage on a local network is disclosed. Computers on a network are configured with a client activity monitoring module that collects activity information including screen captures, keyboard activity, and/or information relating to network communications and sends the collected activity information to a network activity monitor for storage and later retrieval. Each computer on the local network periodically verifies that its client activity monitor module is operable. If a computer fails to send such verification, the system restricts network access by that computer, thus enforcing compliance with the activity monitoring system. The system further provides means for automatically displaying the collected activity information, including through screen savers, automatically changing desktop background images, and pop-up or sidebar windows. The system thus enables review of computer activities for appropriateness by both supervisors or parents as well as by peer users without requiring the reviewer to take affirmative steps to retrieve the activity information.

US Patent:

20170005656, Jan 5, 2017

Filed:

Oct 20, 2015

Appl. No.:

14/918443

Inventors:

- Irvine CA, US
John SCHULER - Gilbert AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 17/687
H01L 49/02
H01L 27/02
H01L 27/06
H01L 27/092
H01L 29/78

Abstract:

A structure for high voltage input stage for deep submicron is provided that does not include native devices. This structure is able to maintain high speed functionality without jeopardizing device reliability or DC (direct current) power consumption. A circuit apparatus includes a first stage that receives an input signal having an input voltage range and generates a first intermediary output signal and a second intermediary output signal. The first stage includes an N-type field effect transistor (NFET) circuit that receives the input signal and generates the first intermediary output signal, where the first intermediary output signal substantially follows the input signal in a first region of the input voltage range and is substantially constant in a second region of the input voltage range. The first stage further includes a P-type field effect transistor (PFET) circuit that receives the input signal and generates the second intermediary output signal, where the second intermediary output signal is substantially constant in the first region of the input voltage range and substantially follows the input signal in the third region of the input voltage range. The circuit apparatus further includes a second stage that receives the first intermediary output signal and the second intermediary output signal and generates a third intermediary output signal.

US Patent:

20140084962, Mar 27, 2014

Filed:

Sep 26, 2012

Appl. No.:

13/627975

Inventors:

- Irvine CA, US
John SCHULER - Gilbert AZ, US

Assignee:

BROADCOM CORPORATION - Irvine CA

International Classification:

H03K 3/00

US Classification:

327108

Abstract:

Aspects of the subject technology allow an output driver to be implemented using one or more transistors having an oxide-breakdown voltage below the output voltage swing of the output driver. The output driver can include one or more source followers, where a source follower provides voltage-level shifting of a voltage before the voltage is supplied to a gate of a transistor to prevent a source-to-gate voltage or a gate-to-source voltage of the transistor from exceeding the oxide-breakdown voltage of the transistor.