John A Schuler

US Patent:

7737798, Jun 15, 2010

Filed:

May 16, 2006

Appl. No.:

11/435810

Inventors:

John A. Schuler - Blaine MN, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03L 7/093

US Classification:

331179, 331177 R, 331 16, 331 34

Abstract:

Various systems and methods for clock generation are disclosed herein. As just one example, a system for clock generation is disclosed that includes a phase/frequency control circuit that provides a feedback control; a multi-range selector circuit that receives the feedback control; and a controlled oscillator that provides an output with a phase and frequency at least in part governed by the multi-range selector circuit and the feedback control. In various instances of the aforementioned embodiments, the controlled oscillator is a ring oscillator relying on inherent capacitance.

US Patent:

7768044, Aug 3, 2010

Filed:

Jul 30, 2004

Appl. No.:

10/903938

Inventors:

Canzhong He - Emmaus PA, US
John A. Schuler - Blaine MN, US
John M. Sharpe - Allentown PA, US
Hong-Ha Vuong - Allentown PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 29/76
H01L 29/94
H01L 21/20
H01L 21/336
H01L 21/8234

US Classification:

257288, 257401, 257296, 257298, 438396, 438197

Abstract:

An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.

US Patent:

8307068, Nov 6, 2012

Filed:

Jun 17, 2009

Appl. No.:

12/486736

Inventors:

John A. Schuler - Chandler AZ, US

Assignee:

Volonics Corporation - Gilbert AZ

International Classification:

G06F 15/173
G06F 15/16
G06F 15/177
G06F 3/048

US Classification:

709224, 709223, 709225, 715867, 715736, 726 11, 726 12

Abstract:

A system for monitoring and regulating computer usage on a local network is disclosed. Computers on a network are configured with a client activity monitoring module that collects activity information including screen captures, keyboard activity, and/or information relating to network communications and sends the collected activity information to a network activity monitor for storage and later retrieval. Each computer on the local network periodically verifies that its client activity monitor module is operable. If a computer fails to send such verification, the system restricts network access by that computer, thus enforcing compliance with the activity monitoring system. The system further provides means for automatically displaying the collected activity information, including through screen savers, automatically changing desktop background images, and pop-up or sidebar windows. The system thus enables review of computer activities for appropriateness by both supervisors or parents as well as by peer users without requiring the reviewer to take affirmative steps to retrieve the activity information.

US Patent:

57572151, May 26, 1998

Filed:

Mar 10, 1997

Appl. No.:

8/814002

Inventors:

Robert John Schuelke - Lakeville MN
John Anthony Schuler - Maplewood MN
Douglas Warren Dean - Eagan MN

Assignee:

VTC Inc. - Bloomington MN

International Classification:

H03K 301
H03K 102

US Classification:

327110

Abstract:

An apparatus conducts current through a two terminal inductive load. The apparatus has a first conduction path, from a first supply voltage to one terminal of the inductive load and a second conduction path from the second terminal of the inductive load to a second supply voltage. The first conduction path includes a switching device that is controlled by a field-effect transistor having a gate terminal, second terminal, and third terminal. The gate terminal of the field-effect transistor is coupled to a reference voltage. The voltage at the second terminal of the field-effect transistor increases when the voltage at the field-effect transistor's third terminal increases.

US Patent:

62462695, Jun 12, 2001

Filed:

Apr 1, 1999

Appl. No.:

9/283154

Inventors:

John A. Schuler - Richfield MN
Craig M. Brannon - Maplewood MN

Assignee:

Agere Systems Guardian Corp. - Miami Lakes FL

International Classification:

H03K 300

US Classification:

327110

Abstract:

A programmable current source is provided for an H-switch to dampen overshoot resulting from a drop in voltage at a node during data transitions. The programmable current source is connected to both nodes of the H-switch on each side of the write head and is responsive to a voltage drop to below a threshold voltage at one node to injecting current into the one node during the period that the node voltage is below the threshold voltage. Preferably, a second programmable current source is connected to both nodes and is responsive to a voltage rise to above a second threshold voltage at the one of the nodes to sink current from the node to dampen undershoot.

US Patent:

20170005656, Jan 5, 2017

Filed:

Oct 20, 2015

Appl. No.:

14/918443

Inventors:

- Irvine CA, US
John SCHULER - Gilbert AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 17/687
H01L 49/02
H01L 27/02
H01L 27/06
H01L 27/092
H01L 29/78

Abstract:

A structure for high voltage input stage for deep submicron is provided that does not include native devices. This structure is able to maintain high speed functionality without jeopardizing device reliability or DC (direct current) power consumption. A circuit apparatus includes a first stage that receives an input signal having an input voltage range and generates a first intermediary output signal and a second intermediary output signal. The first stage includes an N-type field effect transistor (NFET) circuit that receives the input signal and generates the first intermediary output signal, where the first intermediary output signal substantially follows the input signal in a first region of the input voltage range and is substantially constant in a second region of the input voltage range. The first stage further includes a P-type field effect transistor (PFET) circuit that receives the input signal and generates the second intermediary output signal, where the second intermediary output signal is substantially constant in the first region of the input voltage range and substantially follows the input signal in the third region of the input voltage range. The circuit apparatus further includes a second stage that receives the first intermediary output signal and the second intermediary output signal and generates a third intermediary output signal.

US Patent:

20140084962, Mar 27, 2014

Filed:

Sep 26, 2012

Appl. No.:

13/627975

Inventors:

- Irvine CA, US
John SCHULER - Gilbert AZ, US

Assignee:

BROADCOM CORPORATION - Irvine CA

International Classification:

H03K 3/00

US Classification:

327108

Abstract:

Aspects of the subject technology allow an output driver to be implemented using one or more transistors having an oxide-breakdown voltage below the output voltage swing of the output driver. The output driver can include one or more source followers, where a source follower provides voltage-level shifting of a voltage before the voltage is supplied to a gate of a transistor to prevent a source-to-gate voltage or a gate-to-source voltage of the transistor from exceeding the oxide-breakdown voltage of the transistor.