John Spencer Snow

US Patent:

7782990, Aug 24, 2010

Filed:

Sep 27, 2006

Appl. No.:

11/527880

Inventors:

John F. Snow - Taylorsville UT, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 7/00

US Classification:

375355

Abstract:

A method of oversampling a signal in an integrated circuit is disclosed. The method comprises receiving a reference clock signal; generating at least one delayed clock signal, each having a different phase; receiving an input data signal; generating at least one delayed data signal based upon the input data signal; and generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal and a data signal. A circuit for oversampling a signal in an integrated circuit is also disclosed.

US Patent:

7797701, Sep 14, 2010

Filed:

Aug 13, 2004

Appl. No.:

10/917565

Inventors:

John F. Snow - Taylorsville UT, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/46
H04J 3/06

US Classification:

718100, 370503

Abstract:

Method and apparatus for detecting a bit sequence in a data stream is described. In one example, a first memory is configured to process pairs of bit-patterns in the data stream to provide respective pairs of codes from a code table stored in said first memory. A second memory is configured to process pairs of codes from the first memory to provide combination codes from a combination code table stored in the second memory. A third memory is configured to generate detection data in response to a sequence of the combination codes output from the second memory. The first, second, and third memories may be dual-port synchronous memories, such as block random access memory embedded in an integrated circuit. The data stream may be a serial digital interface (SDI) data stream and the bit sequence may be a timing reference signal.