John R Terry

US Patent:

8427958, Apr 23, 2013

Filed:

Apr 30, 2010

Appl. No.:

12/771943

Inventors:

Kung-Ling Ko - Union City CA, US
Surya Prakash Varanasi - Dublin CA, US
Satsheel B. Altekar - San Jose CA, US
John Michael Terry - San Jose CA, US
Venkata Pramod Balakavi - San Jose CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G06F 11/00

US Classification:

370237, 370389, 370474

Abstract:

A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i. e. , a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e. g. , corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network.

US Patent:

8446914, May 21, 2013

Filed:

Apr 22, 2011

Appl. No.:

13/092864

Inventors:

Joseph Juh-En Cheng - Palo Alto CA, US
Wing Cheung - Fremont CA, US
John Michael Terry - San Jose CA, US
Suresh Vobbilisetty - San Jose CA, US
Surya P. Varanasi - Dublin CA, US
Parviz Ghalambor - Los Altos CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

H04L 12/56

US Classification:

370401, 370217, 370244, 370392

Abstract:

One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

US Patent:

20120075999, Mar 29, 2012

Filed:

Sep 28, 2010

Appl. No.:

12/892115

Inventors:

Kung-Ling Ko - Union City CA, US
Surya Prakash Varanasi - Dublin CA, US
Satsheel B. Altekar - San Jose CA, US
John Michael Terry - San Jose CA, US
Vankata Pramod Balakavi - San Jose CA, US

Assignee:

BROCADE COMMUNICATIONS SYSTEMS, INC. - San Jose CA

International Classification:

H04L 12/26

US Classification:

370238, 370252

Abstract:

A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network.

US Patent:

20120110411, May 3, 2012

Filed:

Oct 29, 2010

Appl. No.:

12/916384

Inventors:

Wing Cheung - Fremont CA, US
Joseph Juh-En Cheng - Palo Alto CA, US
John Michael Terry - San Jose CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G11C 29/52
H03M 13/29
H03M 13/05
G11C 15/00
G06F 11/10

US Classification:

714758, 365 491, 365 4917, 714763, 714807, 714E11034

Abstract:

A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.

US Patent:

20130031077, Jan 31, 2013

Filed:

Oct 28, 2011

Appl. No.:

13/284829

Inventors:

Jian Liu - Palo Alto CA, US
Philip Lynn Leichty - Rochester MN, US
How Tung Lim - San Jose CA, US
John Michael Terry - San Jose CA, US
Mahesh Srinivasa Maddury - San Jose CA, US
Wing Cheung - Fremont CA, US
Kung Ling Ko - Union City CA, US

Assignee:

Brocade Communications Systems, Inc. - San Jose CA

International Classification:

G06F 17/30

US Classification:

707706, 707E17108

Abstract:

A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.

US Patent:

20130308649, Nov 21, 2013

Filed:

May 8, 2013

Appl. No.:

13/889637

Inventors:

Wing Cheung - Fremont CA, US
John Michael Terry - San Jose CA, US
Suresh Vobbilisetty - San Jose CA, US
Surya P. Varanasi - Dublin CA, US
Parviz Ghalambor - Los Altos CA, US

Assignee:

BROCADE COMMUNICATIONS SYSTEMS, INC. - San Jose CA

International Classification:

H04L 12/721

US Classification:

370397

Abstract:

One embodiment of the present invention provides a switch. The switch includes a forwarding mechanism and a control mechanism. During operation, the forwarding mechanism forwards frames based on their Ethernet headers. The control mechanism operates the switch in conjunction with a separate physical switch as a single logical switch and assigns a virtual switch identifier to the logical switch, wherein the virtual switch identifier is associated with a link aggregation group.

US Patent:

20160134563, May 12, 2016

Filed:

Jan 19, 2016

Appl. No.:

15/000964

Inventors:

- San Jose CA, US
Phanidhar Koganti - Fremont CA, US
John Michael Terry - San Jose CA, US
Dilip Chatwani - San Jose CA, US

Assignee:

BROCADE COMMUNICATIONS SYSTEMS, INC. - San Jose CA

International Classification:

H04L 12/931
H04H 20/93
H04L 12/26
H04L 12/46

Abstract:

A switch that facilitates remote port mirroring is described. The switch can include an encapsulation mechanism and a forwarding mechanism. The encapsulation mechanism can be configured to encapsulate a copy of a first packet in a second packet, thereby preserving header information (e.g., a VLAN identifier and/or a TRILL header) of the first packet. The forwarding mechanism can be configured to forward the first packet using header information of the first packet, and forward the second packet using header information of the second packet. The second packet can be received at a destination switch which extracts the first packet from the second packet, and sends the first packet on a port which is coupled to a network analyzer.