John R Tyson

US Patent:

D628207, Nov 30, 2010

Filed:

Mar 13, 2009

Appl. No.:

29/333771

Inventors:

Andrew Stanley Potemski - Round Rock TX, US
John Scott Tyson - Austin TX, US
Steven Robert Eustes - Fort Worth CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

3200

US Classification:

D14486

US Patent:

D628208, Nov 30, 2010

Filed:

Mar 13, 2009

Appl. No.:

29/333777

Inventors:

Andrew Stanley Potemski - Round Rock TX, US
John Scott Tyson - Austin TX, US
Matthew Robert Gutierrez - Austin TX, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

3200

US Classification:

D14486

US Patent:

8225256, Jul 17, 2012

Filed:

Apr 15, 2009

Appl. No.:

12/423962

Inventors:

Andrew Stanley Potemski - Round Rock TX, US
John Scott Tyson - Austin TX, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716110, 716 50

Abstract:

Some embodiments of the present invention provide systems and techniques that accelerate project start and tape-out. During operation, a system can receive a set of technology files and a set of libraries. Next, the system can identify deficiencies in the set of technology files and the set of libraries. The system can then construct update utilities that when executed by a computer system cause the computer system to fix the deficiencies in the technology files and the set of libraries. Further, a system can receive a set of checks that are performed by a foundry. Next, the system can construct tape-out scripts that when executed by a computer cause the computer to perform the set of checks on the circuit design. The update utilities and the tape-out scripts can then be provided to a customer with an electronic design automation software to accelerate project start and tape-out.

US Patent:

8413103, Apr 2, 2013

Filed:

Apr 15, 2009

Appl. No.:

12/423955

Inventors:

Andrew Stanley Potemski - Round Rock TX, US
John Scott Tyson - Austin TX, US
Steven Robert Eustes - Fort Worth TX, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 15/04
G06F 17/50

US Classification:

716139, 716100, 716101, 716102, 716106, 716111, 703 22

Abstract:

Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i. e. , software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur.