John Ed Waters

US Patent:

6418505, Jul 9, 2002

Filed:

Dec 17, 1998

Appl. No.:

09/215629

Inventors:

Richard R. Barton - Lexington SC
Peter Washington - Little Mountain SC
John H. Waters - Columbia SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1200

US Classification:

711 2, 709327, 712 32, 713 1

Abstract:

A multi-processor computer system that includes at least one âregularâ processor and one âenhanced modeâ processor. The enhanced mode processor is preferably not turned over to the regular processor, but is initialized to look like an internal or external device, such as a disk drive or the like. In a preferred embodiment, fast access memory that is outside the addressable range of the regular processor is coupled to the enhanced mode processor and accessed through a RAM-disk device driver. In this manner, the amount of fast access memory available to the regular processor is increased.

US Patent:

62090623, Mar 27, 2001

Filed:

Nov 24, 1997

Appl. No.:

8/980876

Inventors:

Vernon K. Boland - Lexington SC
John H. Waters - Columbia SC

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F12/10

US Classification:

711134

Abstract:

A memory management system and method that determines which page or pages in cache memory are likely to be accessed again in the near future by another transaction and designates those pages for recycling so that the pages are maintained in the cache memory for a longer period of time. That is, pages designated for recycling are maintained in the cache, while pages that are not are first replaced. According to the present application, pages in the cache that are likely to be accessed in the near future are those that are accessed by two or more different transactions during their normal residence in the cache.

US Patent:

61294586, Oct 10, 2000

Filed:

Mar 23, 1994

Appl. No.:

8/216907

Inventors:

John H. Waters - Columbia SC
Hiram B. Curry - Charleston SC

Assignee:

AT&T Global Information Solutions Company - Dayton OH

International Classification:

G06F 1134
G06F 1200

US Classification:

395460

Abstract:

A cache optimization method which analyzes an existing cache mapping scheme and determines a new cache mapping scheme that eliminates cache collisions. In a first embodiment, an application is traced while running in its main working set by a processor to obtain cache access statistics for objects within the working set under the first caching scheme. The cache access statistics are analyzed to obtain collision information which reveals lines of operating memory that collide in cache memory. Addresses are assigned to the objects using a cache-miss prediction algorithm. If the cache memory is too small to store all of the objects within the working set, the working set is divided into a plurality of working subsets which each contain a smaller number of objects than the working set. Finally, system calls are executed by the processor to effect the second cache mapping scheme. In a second embodiment, a rearrangement of functions within the application is determined using the cache-miss prediction algorithm and the functions are link edited in accordance with the determined rearrangement.

US Patent:

59182490, Jun 29, 1999

Filed:

Dec 19, 1996

Appl. No.:

8/772039

Inventors:

John S. Cox - Lexington SC
John H. Waters - Columbia SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1200

US Classification:

711203

Abstract:

A non-uniform memory accessing (NUMA) based multiprocessor system that promotes local memory accessing and data migration to local processor nodes. The system includes mechanisms to re-map virtual and physical addresses to promote local memory accessing and implements a least recently used memory allocation mechanism to age non-local memory accesses out of memory to be re-read into local memory, which promotes data migration to local memory on processor nodes.

US Patent:

58601414, Jan 12, 1999

Filed:

Dec 11, 1996

Appl. No.:

8/763918

Inventors:

Peter Washington - Little Mountain SC
John H. Waters - Columbia SC
Richard R. Barton - Lexington SC
Vernon K. Boland - Lexington SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1200

US Classification:

711202

Abstract:

A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.