Jun Q Zhai

US Patent:

7679200, Mar 16, 2010

Filed:

Sep 11, 2007

Appl. No.:

11/853122

Inventors:

Michael Z. Su - Round Rock TX, US
Jaime Bravo - Austin TX, US
Lei Fu - Austin TX, US
Jun Zhai - San Jose CA, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 23/48

US Classification:

257778

Abstract:

Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner.

US Patent:

7745264, Jun 29, 2010

Filed:

Sep 4, 2007

Appl. No.:

11/849545

Inventors:

Jun Zhai - San Jose CA, US
Ranjit Gannamani - San Jose CA, US
Srinivasan Parthasarathy - Mountain View CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/48
H01L 23/28

US Classification:

438127, 257787

Abstract:

Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

US Patent:

7923850, Apr 12, 2011

Filed:

Aug 26, 2008

Appl. No.:

12/198227

Inventors:

Mohammad Khan - Saratoga CA, US
Jun Zhai - San Jose CA, US
Ranjit Gannamani - San Jose CA, US
Raj N. Master - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 23/448
H01L 21/56

US Classification:

257778

Abstract:

Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6. 0 10K.

US Patent:

7989956, Aug 2, 2011

Filed:

Sep 3, 2004

Appl. No.:

10/933533

Inventors:

Jun Zhai - Mountain View CA, US
Fei Wang - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29/66

US Classification:

257774, 257E23155

Abstract:

An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems.

US Patent:

8008133, Aug 30, 2011

Filed:

Feb 11, 2008

Appl. No.:

12/029305

Inventors:

Eric Tosaya - Fremont CA, US
Jun Zhai - San Jose CA, US
Chia-Ken Leong - Santa Clara CA, US
Tom Ley - Cupertino CA, US

Assignee:

Globalfoundries Inc. - Grand Cayman

International Classification:

H01L 21/00

US Classification:

438126, 438121, 438127, 257E21499

Abstract:

Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

US Patent:

8301668, Oct 30, 2012

Filed:

Apr 18, 2008

Appl. No.:

12/105936

Inventors:

Wenbin He - Foster City CA, US
Wenfeng Li - Foster City CA, US
Jun Zhai - San Mateo CA, US
Petter Ivmark - San Francisco CA, US
Gauri Tikekar - Sunnyvale CA, US

Assignee:

Actuate Corporation - San Mateo CA

International Classification:

G06F 17/30

US Classification:

707804, 707755, 707756, 707791, 707793, 707802, 707803, 707705

Abstract:

In accordance with one aspect of the invention, methods and apparatus for providing information for use in generating or modifying an expression are disclosed. Input from a user is received within an expression. A list of one or more suggestions is provided in response to the input. A selection of one of the suggestions in the list is received. The expression is then built to include the selection.

US Patent:

8405187, Mar 26, 2013

Filed:

Jun 10, 2011

Appl. No.:

13/158048

Inventors:

Eric Tosaya - Fremont CA, US
Jun Zhai - San Jose CA, US
Chia-Ken Leong - Santa Clara CA, US
Tom Ley - Cupertino CA, US

Assignee:

Globalfoundries Inc. - Grand Cayman

International Classification:

H01L 29/00

US Classification:

257528, 257704, 257E21499

Abstract:

Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate.

US Patent:

8486767, Jul 16, 2013

Filed:

Jun 23, 2011

Appl. No.:

13/166988

Inventors:

Jun Zhai - Mountain View CA, US
Fei Wang - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/82

US Classification:

438128, 257774, 257E23155

Abstract:

An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems.