Johnson C Tan

US Patent:

6961280, Nov 1, 2005

Filed:

Dec 8, 2003

Appl. No.:

10/731279

Inventors:

Philip Pan - Fremont CA, US
Chiakang Sung - Milpitas CA, US
Joseph Huang - San Jose CA, US
Yan Chong - San Jose CA, US
Johnson Tan - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C008/00

US Classification:

36523002, 36523001, 36523008, 711 3, 711211

Abstract:

Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.

US Patent:

7589556, Sep 15, 2009

Filed:

Oct 26, 2007

Appl. No.:

11/925717

Inventors:

Johnson Tan - Mountain View CA, US
Andrew Bellis - Guildford, GB
Philip Clarke - Leatherhead, GB
Yan Chong - San Jose CA, US
Joseph Huang - Morgan Hill CA, US
Michael H. M. Chu - Fremont CA, US
Chiakang Sung - Milpitas CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 7/38

US Classification:

326 40, 326 46, 326 38

Abstract:

Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

US Patent:

6912164, Jun 28, 2005

Filed:

Aug 22, 2003

Appl. No.:

10/646538

Inventors:

Yan Chong - Mountain View CA, US
Chiakang Sung - Milpitas CA, US
Joseph Huang - San Jose CA, US
Philip Pan - Fremont CA, US
Johnson Tan - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C007/00

US Classification:

36518902, 36518912, 365221

Abstract:

Techniques for preloading data into memory blocks on a programmable circuit are provided. Memory blocks on the a programmable circuit each have dedicated circuitry that loads data into the memory block. The dedicated circuit also generates memory addresses used to load the data into the memory block. The dedicated circuitry associated with each memory block reduces demand on the routing resources. A user can preload data into the memory blocks prior to user mode. A user can also prevent data from being preloaded into one or more of the memory blocks prior to user mode. By allowing the user to program some or all of the memory blocks prior to user mode, the time needed to a program the memory blocks prior to user mode can be substantially reduced.