Jon D Cheek

US Patent:

5904534, May 18, 1999

Filed:

Aug 14, 1998

Appl. No.:

9/134702

Inventors:

Jon D. Cheek - Round Rock TX
Derick J. Wristers - Austin TX
H. Jim Fulford - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L21/336;21/76

US Classification:

438305

Abstract:

An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

US Patent:

6346426, Feb 12, 2002

Filed:

Nov 17, 2000

Appl. No.:

09/716181

Inventors:

Anthony J. Toprac - Austin TX
Derick J. Wristers - Austin TX
Jon D. Cheek - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 2100

US Classification:

438 8, 73105

Abstract:

A method for characterizing semiconductor device performance variations includes processing a wafer in a processing line to form a feature on the wafer; measuring a physical critical dimension of the feature in a first metrology tool to generate a first critical dimension measurement; measuring the physical critical dimension of the feature in a second metrology tool to generate a second critical dimension measurement independent of the first critical dimension measurement; determining an effective critical dimension of the feature in a third metrology tool to generate a third critical dimension measurement; and comparing the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools. A system for characterizing semiconductor device performance variations includes a processing line, first, second, and third metrology tools, and a process controller. The processing line is adapted to process a wafer to form a feature on the wafer.

US Patent:

6358803, Mar 19, 2002

Filed:

Jan 21, 2000

Appl. No.:

09/489369

Inventors:

Mark Michael - Cedar Park TX
Jon D. Cheek - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438301, 438303, 438305

Abstract:

Methods of fabricating source/drain regions and transistors incorporating the same are provided. In one aspect, a method of fabricating a source/drain region in a substrate is provided that includes forming a stack on the substrate with a gate electrode and an insulating layer positioned on the gate electrode that has etch selectivity to the gate electrode. A first doped region is formed in the substrate adjacent to the stack with a first horizontal junction. A second doped region is formed in the substrate that overlaps the first doped region and has a second horizontal junction positioned beneath the first horizontal junction. An implant of impurity ions into the substrate is performed to establish a third doped region that overlaps the second doped region and has a third horizontal junction positioned beneath the second horizontal junction. The insulating layer prevents impurity ions from substantially penetrating through the gate electrode. The substrate is heated to activate the first, the second and the third doped regions.

US Patent:

6359461, Mar 19, 2002

Filed:

Feb 10, 1998

Appl. No.:

09/021094

Inventors:

John J. Bush - Leander TX
Jon D. Cheek - Round Rock TX
H. Jim Fulford - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3126

US Classification:

324769, 324768

Abstract:

The present invention advantageously provides a test structure and method for determining the distinct characteristics of each transistor arranged in a densely packed configuration with other transistors. Formation of the test structure first involves forming gate conductors according to the configuration of the semiconductor topography whose device properties are being determined. That is, closely spaced gate conductors having relatively small lateral widths, i. e. , physical gate lengths, are formed above a semiconductor substrate. All of the gate conductors except the one being tested are then etched from above the substrate. Source/drain implants which are self-aligned to the opposed sidewall surfaces of the gate conductor retained above the substrate are forwarded into the substrate. Absent the other gate conductors, the resulting source/drain regions may each have a larger lateral width greater than the distance between the pre-existing gate conductors. As such, the lateral width of contacts formed through an interlevel dielectric to the source/drain regions may be made significantly less than the lateral width of each source/drain region.

US Patent:

6372587, Apr 16, 2002

Filed:

May 10, 2000

Appl. No.:

09/568069

Inventors:

Jon D. Cheek - Round Rock TX
Scott D. Luning - Austin TX
Derick J. Wristers - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21336

US Classification:

438302, 438303

Abstract:

A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness above the surface and having an edge disposed a distance from the first edge of the structure. The method also includes implanting the halo implant at an angle with respect to a direction perpendicular to the surface, wherein the tangent of the angle is at least the ratio of the distance to the thickness.

US Patent:

6383872, May 7, 2002

Filed:

Sep 25, 1998

Appl. No.:

09/160829

Inventors:

Daniel Kadosh - Austin TX
Mark I. Gardner - Cedar Creek TX
Jon D. Cheek - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21335

US Classification:

438279, 438596, 438947

Abstract:

An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

US Patent:

6399493, Jun 4, 2002

Filed:

May 17, 2001

Appl. No.:

09/860141

Inventors:

Robert Dawson - Austin TX
Jon D. Cheek - Round Rock TX
John G. Pellerin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438682, 438683, 438586, 438592

Abstract:

Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.

US Patent:

6403979, Jun 11, 2002

Filed:

Feb 9, 2001

Appl. No.:

09/780834

Inventors:

Daniel Kadosh - Austin TX
Jon D. Cheek - Round Rock TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 2358

US Classification:

257 48

Abstract:

A test structure for use in determining an effective channel length of a transistor is disclosed herein. The test structure comprises a first resistor comprised of a first doped region formed in a semiconducting substrate between a first pair of spaced-apart structures positioned above the substrate, the first resistor having a first width defined by the spacing between the first pair of structures, a second resistor comprised of a second doped region formed in the substrate between a second pair of spaced-apart structures positioned above the substrate, the second resistor having a second width defined by the spacing between the second pair of structures, the second width being greater than the first width, and a plurality of conductive contacts electrically coupled to each of the first and second doped regions. The method disclosed herein comprises determining the extent of lateral encroachment of the doped regions under the structures based upon the following formula: w=(R W W )/(R -R ). The effective channel length of the transistor may be determined by subtracting the w value from the length of the gate electrode.

Address:

2910 Kinloch Dr, Cedar Park, TX 78613

VIN:

2GCEC13J471540652

Make:

CHEVROLET

Model:

SILVERADO 1500

Year:

2007