Jon E Josephson

US Patent:

6532580, Mar 11, 2003

Filed:

Feb 18, 2000

Appl. No.:

09/507034

Inventors:

Jon Eric Josephson - Fort Collins CO
Jeffrey P Witte - Ft Collins CO
Rex Mark Petersen - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 10, 716 12, 716 2

Abstract:

A method and system for inserting in-place interconnect repeaters along the paths of interconnects of an integrated circuit is presented. The integrated circuit includes an interconnect layer on which an interconnect is routed, a silicon layer in which repeaters are implemented, and zero or more intervening layers. In accordance with the invention, reserved metal areas are defined on each intervening layer that resides between the interconnect layer and the repeater layer. Each interconnect net that requires a repeater for performance reasons is assigned to a repeater location. A repeater buffer is inserted at the assigned repeater locations. The interconnect net is cut into first and second subnets, which are then respectively connected through the reserved metal areas of the intervening layers to the respective input and output port of the repeater buffer.

US Patent:

7323915, Jan 29, 2008

Filed:

Jan 19, 2006

Appl. No.:

11/335749

Inventors:

Jon E. Josephson - Minneapolis MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

H03L 7/06

US Classification:

327149, 327158

Abstract:

A DLL includes a control module coupled with a phase detect signal. The phase detect signal is used by a control module to generate feedback and output select signals. The feedback and output select signals are each coupled to a multiplexer. Each multiplexer is coupled to a Multi-Tap Delay Line (MTDL). The MTDL provides a plurality of delayed signals that are selectable by the two multiplexers. The first multiplexer, coupled to the feedback select signal, selects a feedback clock signal. The second multiplexer, coupled to the output select signal, select a DLL output signal. The control module may receive other signals, such as a delay select signal, that may be used to program or set the delay of the output signal. In addition, a plurality of output signals may be available from the DLL.

US Patent:

6408426, Jun 18, 2002

Filed:

Feb 19, 2000

Appl. No.:

09/507442

Inventors:

Jon Eric Josephson - Fort Collins CO
John D Wanek - Denver CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 12, 716 9, 716 10

Abstract:

A method and system for determining locations of interconnect repeater farms in the physical design of an integrated circuit is presented. The optimal unconstrained repeater locations are calculated for a given routing list of interconnect nets. Repeater farms are defined in areas of concentration of the calculated optimal unconstrained repeater locations. The optimal constrained repeater locations are then calculated such that the repeater locations are constrained to the repeater farms. A set of sub-optimal interconnect nets which are hurt the most from the repeater farm constraint are selected. The optimal unconstrained repeater locations for the selected set of sub-optimal interconnect nets are then calculated and additional repeater farms are defined to encompass areas of concentration of the optimal repeater locations of the sub-optimal interconnect nets. The process is repeated until desired performance gain is achieved.