Jonathan Harris

US Patent:

6345302, Feb 5, 2002

Filed:

Aug 21, 2000

Appl. No.:

09/641762

Inventors:

Toby D. Bennett - Adelphi MD
Donald J. Davis - Severn MD
Jonathan C. Harris - Crofton MD
Ian D. Miller - Columbia MD

Assignee:

TSI TelSys, Inc. - Columbia MD

International Classification:

G06F 1516

US Classification:

709236, 709230, 709238, 709242, 709243, 709250

Abstract:

A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

US Patent:

6952817, Oct 4, 2005

Filed:

Dec 4, 2002

Appl. No.:

10/310336

Inventors:

Jonathan C. Harris - Ellicott City MD, US
Stephen G. Edwards - Woodbine MD, US
James E. Jensen - Ellicott CIty MD, US
Andreas B. Kollegger - Baltimore MD, US
Ian D. Miller - Charlotte NC, US
Christopher R. S. Schanck - Marriottsville MD, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F017/50

US Classification:

716 18, 716 3, 717140, 717155, 717156, 717161

Abstract:

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (, and ). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model ().

US Patent:

6122670, Sep 19, 2000

Filed:

Oct 30, 1997

Appl. No.:

8/960837

Inventors:

Toby D. Bennett - Adelphi MD
Donald J. Davis - Severn MD
Jonathan C. Harris - Crofton MD
Ian D. Miller - Columbia MD

Assignee:

TSI Telsys, Inc. - Columbia MD

International Classification:

G06F 1338
G06F 1517

US Classification:

709236

Abstract:

A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

US Patent:

59208821, Jul 6, 1999

Filed:

Nov 21, 1996

Appl. No.:

8/752940

Inventors:

Toby D. Bennett - Hyattsville MD
James W. Bishop - Glendale MD
Donald J. Davis - Severn MD
Jonathan C. Harris - Crofton MD

Assignee:

TSI TelSys Inc. - Columbia MD

International Classification:

G06F 1300

US Classification:

711101

Abstract:

A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.

US Patent:

62303074, May 8, 2001

Filed:

Jan 26, 1998

Appl. No.:

9/013186

Inventors:

Donald J. Davis - Severn MD
Toby D. Bennett - Adelphi MD
Jonathan C. Harris - Crofton MD
Ian D. Miller - Columbia MD
Stephen G. Edwards - Laurel MD

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1750
G06F 738

US Classification:

716 16

Abstract:

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.