Jonathan I Mills

US Patent:

8219506, Jul 10, 2012

Filed:

Nov 13, 2007

Appl. No.:

12/514897

Inventors:

Russell C. Eberhart - Indianapolis IN, US
Jonathan W. Mills - Bloomington IN, US
Bryce Himebaugh - Bloomington IN, US
Xiaohui Hu - Indianapolis IN, US

Assignee:

Indiana University Research and Technology Corp. - Indianapolis IN

International Classification:

G06G 7/00

US Classification:

706 3

Abstract:

A method is used to configure an extended analog computer for use as an application controller. The method includes selecting input pins from among a plurality of pins in a continuous sheet processor, selecting an arrangement of intermediate and output pins from among the remaining pins in the plurality of pins in the continuous sheet processor, applying a pattern data set to the input pins, using an evolutionary algorithm, coupling current sources and sinks to the intermediate and output pins, measuring an error between an output and its expected value, and continuing to select intermediate and output pin arrangements, apply pattern data sets, and measure errors until a configuration threshold is met.

US Patent:

20130159008, Jun 20, 2013

Filed:

Dec 20, 2011

Appl. No.:

13/331745

Inventors:

Jonathan Mills - Loveland OH, US
Thomas M. Rempe - Wyoming OH, US
Chuck Eliasen - Cincinnati OH, US
Anish Bole - Dayton OH, US
Robyn M. Andersen - Omaha NE, US
Valerie Stribbling - Atlanta GA, US

Assignee:

FIRST DATA CORPORATION - Greenwood Village CO

International Classification:

G06Q 50/22

US Classification:

705 2

Abstract:

Embodiments of the invention provide systems and method for verifying healthcare visits. Location verification information may be received from a portable device by a verification system that includes one or more computers. The portable device may be associated with an individual directed to provide a healthcare service to a patient during a healthcare visit, and the location verification information may be collected by the portable device. The verification system may compare at least a portion of the received information to stored information associated with the patient. Based at least in part upon the comparison, the verification system may determine whether the healthcare visit was performed at an approved service location for the patient.

US Patent:

59173386, Jun 29, 1999

Filed:

Mar 25, 1998

Appl. No.:

9/047753

Inventors:

Jonathan W. Mills - Bloomington IN

Assignee:

Indiana University - Bloomington IN

International Classification:

H03K 1900

US Classification:

326 59

Abstract:

A one-diode circuit for negated implication (. about. fwdarw. ) is derived from a 12-transistor Lukasiewicz implication circuit (. fwdarw. ). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (. English Pound. LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower. English Pound. LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor. English Pound. LA contains 1,990 implications. Both. English Pound. LAs double the number of inputs per pin on the IC package. Very dense. English Pound. LAs make.

US Patent:

57709661, Jun 23, 1998

Filed:

Jan 15, 1997

Appl. No.:

8/783196

Inventors:

Jonathan W. Mills - Bloomington IN

Assignee:

Indiana University Foundation - Bloomington IN

International Classification:

H03K 302

US Classification:

327355

Abstract:

A one-diode circuit for negated implication (. about. fwdarw. ) is derived from a 12-transistor Lukasiewicz implication circuit (. fwdarw. ). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (. English Pound. LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower. English Pound. LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor. English Pound. LA contains 1,990 implications. Both. English Pound. LAs double the number of inputs per pin on the IC package. Very dense. English Pound. LAs make.

US Patent:

51932067, Mar 9, 1993

Filed:

Aug 10, 1992

Appl. No.:

7/926366

Inventors:

Jonathan W. Mills - Bloomington IN

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 922

US Classification:

395800

Abstract:

A LOW RISC (reduced instruction set computer) III microprocessor reduces the number of branches taken during execution of logic, functional, and symbolic programs to increase the efficiency and effectiveness of pipelined execution memory interleave, and reduces the complexity of RISC architectures. The LOW RISC III is a 40-bit, 4-stage pipelined processor which is pipelined with each stage operating synchronously in parallel. Pipeline breaks are reduced by moving partial unification and trail checking into hardware, and eliminating many short branches by conditional execution of the various instructions.