Jonathan W Owen

US Patent:

7870407, Jan 11, 2011

Filed:

May 18, 2007

Appl. No.:

11/750365

Inventors:

Alex Branover - Brookline MA, US
Frank P. Helms - Austin TX, US
Jonathan M. Owen - Northboro MA, US
Kurt Lewchuk - Austin TX, US
Maurice Steinman - Marlborough MA, US
Paul Mackey - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32

US Classification:

713323, 713300, 713310, 713320, 713330

Abstract:

A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

US Patent:

8291249, Oct 16, 2012

Filed:

Sep 25, 2009

Appl. No.:

12/566930

Inventors:

Alexander Branover - Chestnut Hill MA, US
Denis Rystsov - Arlington MA, US
Maurice B. Steinman - Marlborough MA, US
Jonathan M. Owen - Northborough MA, US
Denis J. Foley - Shrewsbury MA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 1/32

US Classification:

713323, 713320

Abstract:

A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

US Patent:

8412971, Apr 2, 2013

Filed:

May 11, 2010

Appl. No.:

12/777657

Inventors:

Alexander Branover - Chestnut Hill MA, US
Norman M. Hack - Pflugerville TX, US
Maurice B. Steinman - Marlborough MA, US
John Kalamatianos - Arlington MA, US
Jonathan M. Owen - Northborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713324, 713323, 713330, 711118

Abstract:

A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

US Patent:

20110112798, May 12, 2011

Filed:

Nov 23, 2009

Appl. No.:

12/623997

Inventors:

Alexander Branover - Chestnut Hill MA, US
Maurice B. Steinman - Marlborough MA, US
Jonathan D. Hauke - Lexington MA, US
Jonathan M. Owen - Northborough MA, US

International Classification:

G21C 17/00

US Classification:

702186

Abstract:

A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.