Jonathan M Owen

US Patent:

6665742, Dec 16, 2003

Filed:

Jan 31, 2001

Appl. No.:

09/773777

Inventors:

Jonathan M. Owen - Northboro MA
Mark D. Hummel - Franklin MA
Derrick R. Meyer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
API Networks, Inc. - Concord MA

International Classification:

G06F 1310

US Classification:

710 10, 710 3, 710 8, 710 9, 710104, 713 1, 713100

Abstract:

A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed.

US Patent:

6721813, Apr 13, 2004

Filed:

Jan 30, 2001

Appl. No.:

09/774148

Inventors:

Jonathan M. Owen - Northboro MA
Mark D. Hummel - Franklin MA
James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

710 6, 710 5, 710 7, 710 20, 710 21, 710 40, 710 41, 710 45, 710 58, 710 61, 710107, 710129, 711141, 711151, 712 8, 712 30

Abstract:

A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e. g. , modem, sound card, etc. ). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing nodes memory, wherein the non-coherent write transaction is a posted write transaction. The I/O node may dispatch the non-coherent write transaction directed to the host bridge.

US Patent:

6745272, Jun 1, 2004

Filed:

Apr 4, 2001

Appl. No.:

09/826262

Inventors:

Jonathan M. Owen - Northboro MA
Mark D. Hummel - Franklin MA
Derrick R. Meyer - Austin TX
James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
API Networks, Inc. - Concord MA

International Classification:

G06F 1300

US Classification:

710107, 710306, 711154

Abstract:

A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.

US Patent:

6751684, Jun 15, 2004

Filed:

Dec 21, 2000

Appl. No.:

09/746109

Inventors:

Jonathan M. Owen - Northboro MA 01532
Mark D. Hummel - Franklin MA 02038

International Classification:

G06F 300

US Classification:

710 29, 710 33, 710 41, 709209, 709233, 709232, 714776, 370231, 370232, 370233, 370285, 37039541

Abstract:

A method is provided for fairly allocating bandwidth to a plurality of devices connected to a communication link implemented as a plurality of point-to-point links. The point-to-point links interconnect the devices in a daisy chain fashion. Each device is configured to transmit locally generated packets and to forward packets received from downstream devices onto one of the point-to-point links. The rate at which each device transmits local packets relative to forwarding received packets is referred to as the devices insertion rate. A fair bandwidth allocation algorithm is implemented in each (upstream) device to determine the highest packet issue rate of the devices which are downstream of that (upstream) device. The packet issue rate of a downstream device is the number of local packets associated with the downstream device that are received at the upstream device relative to the total number of packets received at the upstream device. By monitoring the total flow of packets received at the upstream device, the highest packet issue rate of the respective packet issue rates of the downstream devices may be determined.

US Patent:

6760838, Jul 6, 2004

Filed:

Jan 31, 2001

Appl. No.:

09/773763

Inventors:

Jonathan M. Owen - Northboro MA
Mark D. Hummel - Franklin MA
Derrick R. Meyer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
API NetWorks, Inc. - Concord MA

International Classification:

G06F 15177

US Classification:

713 1, 713 2, 709250, 709251, 709252, 709253, 710 8, 710 9, 710 10

Abstract:

A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed.

US Patent:

6950438, Sep 27, 2005

Filed:

Aug 17, 2000

Appl. No.:

09/640602

Inventors:

Jonathan M. Owen - Northborough MA, US
Mark D. Hummel - Franklin MA, US
James B. Keller - Redwood City CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Alpha Processor, Inc. - Concord MA

International Classification:

H04L012/00

US Classification:

370409, 370464

Abstract:

A computer system employs virtual channels and allocates different resources to the virtual channels. More particularly, the computer system provides a posted commands virtual channel separate from the non-posted commands virtual channel for routing posted and non-posted commands or requests through coherent and noncoherent fabrics within the computer system. Because separate resources are allocated to the virtual channels in the computer system, posted requests may be allowed to become unordered with other requests from the same source. Implementation of a separate posted commands virtual channel may allow the computer system to maintain compatibility with I/O systems in which posted write requests may become unordered with previous posted requests (e. g. , the Peripheral Component Interconnect Bus, or PCI). Implementation of the separate posted commands virtual channel thus may assist in providing deadlock-free operation.

US Patent:

7069361, Jun 27, 2006

Filed:

Apr 23, 2001

Appl. No.:

09/840449

Inventors:

Jonathan M. Owen - Northboro MA, US
Mark D. Hummel - Franklin MA, US
Derrick R. Meyer - Austin TX, US
James B. Keller - Palo Alto CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
API NetWorks, Inc. - Concord MA

International Classification:

G06F 13/00

US Classification:

710107, 710306, 711141

Abstract:

A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.

US Patent:

7287105, Oct 23, 2007

Filed:

Jan 12, 2005

Appl. No.:

11/033561

Inventors:

Jonathan Mercer Owen - Northboro MA, US
Mark Douglas Hummel - Franklin MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 7/10
G06F 1/12
H04L 7/02

US Classification:

710 52, 710 61, 713400, 375354, 36518901, 36518908

Abstract:

Precise estimation of latency is attained based on identifying that a receive clock is configured to operate only at prescribed available frequencies. A receive buffer circuit includes buffer control logic configured for reading a selected number of the buffer entries based on a detected number of receive clock edges within one local clock cycle. Valid data is identified based on the number of clock edges exceeding a selected threshold. A selected pointer offset is obtained from a lookahead table, specifying multiple pointer offsets for accommodating latency encountered at respective prescribed available frequencies, based on matching the determined frequency to one of the prescribed available frequencies. The selected pointer offset is added to a read pointer to offset the latency encountered from edge detection.