Jonathon R Ramsey

US Patent:

20170161206, Jun 8, 2017

Filed:

Feb 20, 2017

Appl. No.:

15/437400

Inventors:

- Santa Clara CA, US
John MASHEY - Portola Valley CA, US
Mark HAIRGROVE - San Jose CA, US
Lucien DUNNING - Santa Clara CA, US
Jonathon Stuart Ramsey EVANS - Santa Clara CA, US
Samuel H. DUNCAN - Arlington MA, US
Cameron BUSCHARDT - Round Rock TX, US
Brian FAHS - Fremont CA, US

International Classification:

G06F 12/1027
G06F 9/46

Abstract:

One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.