Jong Han Lee

US Patent:

6728140, Apr 27, 2004

Filed:

Dec 5, 2001

Appl. No.:

10/011157

Inventors:

Kyung Joon Han - Palo Alto CA
Joo Weon Park - Pleasanton CA
Dung Tran - San Jose CA
Steve K. Hsia - San Jose CA
Jong Seuk Lee - Palo Alto CA
Dae Hyun Kim - Fremont CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518524, 36518526, 3651853, 36518529

Abstract:

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

US Patent:

6873004, Mar 29, 2005

Filed:

Feb 4, 2003

Appl. No.:

10/358645

Inventors:

Kyung Joon Han - Palo Alto CA, US
Steve K. Hsia - San Jose CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Palo Alto CA, US

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

H01L029/788

US Classification:

257315, 257E293, 257 6, 438266, 438286, 438302, 438525

Abstract:

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

US Patent:

7094089, Aug 22, 2006

Filed:

Mar 12, 2004

Appl. No.:

10/799403

Inventors:

Bartley K. Andre - Menlo Park CA, US
Jonathan P. Ive - San Francisco CA, US
Jong Min Lee - San Francisco CA, US
Kan Lim - Sunnyvale CA, US

Assignee:

Apple Computer, Inc. - Cupertino CA

International Classification:

H01R 21/00

US Classification:

439218, 439607

Abstract:

A DC connector arrangement is disclosed. The DC connector arrangement includes a DC plug and a DC receptacle that are configured to engage one another at more than one position. The DC plug and DC receptacle are also configured with a small contact distance to minimize the insertion and extraction forces that occur between the DC plug and the DC receptacle.

US Patent:

8093576, Jan 10, 2012

Filed:

Nov 30, 2009

Appl. No.:

12/627128

Inventors:

Jong Won Lee - San Francisco CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 47/00

US Classification:

257 4, 257 5, 257 42, 257E45002, 438102, 438 95, 438626

Abstract:

A method of forming a semiconductor device may comprise forming a memory portion, forming a carbon film, depositing insulation to at least partially cover the carbon film, and terminating patterned removal of the insulation at the carbon film during a fabrication process.

US Patent:

20100327413, Dec 30, 2010

Filed:

May 2, 2008

Appl. No.:

12/595234

Inventors:

Jong Pil Lee - San Ramon CA, US
Seiji Kawaguchi - San Jose CA, US
Camelia Rusu - Fremont CA, US
Zhisong Huang - Fremont CA, US
Mukund Srinivasan - Fremont CA, US
Eric Hudson - Berkeley CA, US
Aaron Eppler - Fremont CA, US

Assignee:

LAM RESEARCH CORPORATION - Fremont CA

International Classification:

H01L 29/00
H01L 21/3065
C23F 1/08
H01L 21/306

US Classification:

257618, 438710, 438725, 15634524, 257E21218, 257E29001

Abstract:

A method for opening a carbon-based hardmask layer formed on an etch layer over a substrate is provided. The hardmask layer is disposed below a patterned mask. The substrate is placed in a plasma processing chamber. The hardmask layer is opened by flowing a hardmask opening gas including a COS component into the plasma chamber, forming a plasma from the hardmask opening gas, and stopping the flow of the hardmask opening gas. The hardmask layer may be made of amorphous carbon, or made of spun-on carbon, and the hardmask opening gas may further include O.

US Patent:

20120225534, Sep 6, 2012

Filed:

May 15, 2012

Appl. No.:

13/472053

Inventors:

Jong Won Lee - San Francisco CA, US
Gianpaolo Spadini - Campbell CA, US
Derchang Kau - Cupertino CA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 45/00

US Classification:

438382, 257E45002

Abstract:

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

US Patent:

20120282752, Nov 8, 2012

Filed:

Jul 20, 2012

Appl. No.:

13/553948

Inventors:

Jong Won Lee - San Francisco CA, US
DerChang Kau - Cupertino CA, US
Gianpaolo Spadini - Campbell CA, US

International Classification:

H01L 21/8239

US Classification:

438382, 257E21004, 257E21645

Abstract:

In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

US Patent:

20130283936, Oct 31, 2013

Filed:

Apr 27, 2012

Appl. No.:

13/458048

Inventors:

Fabio Pellizzer - Cornate D'adda, IT
Innocenzo Tortorelli - Moncalieri, IT
Christina Papagianni - San Jose CA, US
Gianpaolo Spadini - Scotts Valley CA, US
Jong Won Lee - San Francisco CA, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

G01N 33/00
H01B 13/00
C23C 16/455
B05D 5/12

US Classification:

73866, 427 58, 216 13

Abstract:

Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.

Address:

7001 NE 186 Pl APT 103, Kenmore, WA 98028

VIN:

JHLRE48537C059118

Make:

HONDA

Model:

CR-V

Year:

2007