Jonghee H Han

US Patent:

6839288, Jan 4, 2005

Filed:

Nov 12, 2003

Appl. No.:

10/706146

Inventors:

Jung Pill Kim - Cary NC, US
Jonghee Han - Cary NC, US
Stephen Camacho - Durham NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 700

US Classification:

36518905, 365195

Abstract:

Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced by preventing the outputs of the latch circuits from changing when an invalid command is detected. For some embodiments, an invalid command detector is provided that generates an invalid command signal used to inhibit latch circuits, in response to detecting an invalid command.

US Patent:

6847566, Jan 25, 2005

Filed:

Oct 23, 2003

Appl. No.:

10/692119

Inventors:

Jonghee Han - Cary NC, US
Jung Pill Kim - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 700

US Classification:

365203, 365222, 365205

Abstract:

Methods and circuit configurations for multiple recycling of charge during a refresh operation in a memory device, such as a dynamic random access memory (DRAM) device, are provided. Charge from one or more power lines of a first array of bit line sense amplifiers involved in a first refresh operation may be transferred to one or more power lines of at least second and third arrays of bit line sense amplifiers involved in subsequent refresh operations.

US Patent:

6888767, May 3, 2005

Filed:

Nov 26, 2003

Appl. No.:

10/723211

Inventors:

Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C007/00

US Classification:

365203, 365204, 365207, 365226

Abstract:

Sensing operations involving a first array of bit line sense amplifiers (BLSAs) may be powered by an upper reference voltage and a first intermediate voltage and the first array may be precharged to a voltage level therebetween. Sensing operations involving a second array of BLSAs may be powered by a second intermediate voltage (greater than the first intermediate voltage) and a lower reference voltage and the second array may be precharged to a voltage level therebetween. After precharge, charge may be transferred from a second power line of the first array to a first power line of the second array. Subsequently, the second power line of the first array may be coupled to a power supply node at the first intermediate voltage level and the first power line of the second array may be coupled to a power supply node at the second intermediate voltage level.

US Patent:

6891763, May 10, 2005

Filed:

Dec 23, 2003

Appl. No.:

10/744804

Inventors:

Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C007/00

US Classification:

36518905, 36523008

Abstract:

Embodiments of the present invention are illustrated in a random access memory. In one embodiment, a random access memory comprises an array of memory cells, a write circuit, and an input buffer configured to receive data and pass the received data to the write circuit that writes the received data into the array of memory cells. The input buffer comprises a differential amplifier configured to receive the data and in response to the received data supply a first signal and a second signal that is the compliment of the first signal. The input buffer also comprises a first transistor configured to be controlled by the first signal and a second transistor configured to be controlled by the second signal. The first transistor and the second transistor are turned on to provide a current path through the first transistor and the second transistor to change the first signal in response to a transition in the received data.

US Patent:

6934197, Aug 23, 2005

Filed:

Oct 10, 2003

Appl. No.:

10/683768

Inventors:

Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C016/04

US Classification:

36518905, 365207, 36518909

Abstract:

A method and circuit configuration for digitizing data and control signals using an input buffer in a dynamic random access memory (DRAM) device. In one embodiment, the input buffer includes buffer modules having a differential amplifier with a first input responsive to an input signal and a second input responsive to a reference voltage, a common source stage, and an output stage and a source of a bias voltage controlling impedance of the common source stage, wherein the reference voltage defines the amplitude of the bias voltage.

US Patent:

7031205, Apr 18, 2006

Filed:

Sep 29, 2003

Appl. No.:

10/674177

Inventors:

Jonghee Han - Cary NC, US
Alexander George - Durham NC, US
Torsten Partsch - Raleigh NC, US

Assignee:

Infineon Technologies North America Corp. - San Jose CA

International Classification:

G11C 7/00

US Classification:

365193, 365233, 3652335, 36518905

Abstract:

A random access memory includes a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal, and a second circuit configured to receive the strobe signal to latch data into the second circuit in response to the strobe signal, and to receive the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal. The first circuit includes an enable circuit configured to provide an enable signal and a buffer circuit configured to receive the strobe signal and the enable signal and provide the pulses in response to the enable signal and the strobe signal. The enable circuit is configured to receive the pulses from the buffer circuit and stop providing the enable signal to the buffer circuit in response to receiving the pulses.

US Patent:

7064586, Jun 20, 2006

Filed:

Dec 19, 2003

Appl. No.:

10/739097

Inventors:

Jung Pill Kim - Cary NC, US
Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies, AG - Munich

International Classification:

H03K 5/153
H03K 5/22

US Classification:

327 77, 327 89

Abstract:

A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.

US Patent:

7120067, Oct 10, 2006

Filed:

Mar 14, 2005

Appl. No.:

11/079726

Inventors:

Jonghee Han - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 7/00

US Classification:

36518905, 365193, 365194

Abstract:

A circuit for latching data into a memory includes a receiver, a delay, and a selector. The receiver is configured for receiving a data signal, and the delay is configured to delay the data signal to provide a delayed data signal. The selector is configured to receive the delayed data signal, a data strobe signal, and an inverted data strobe signal and provide a first strobe signal and a second strobe signal in response to the delayed data signal, the data strobe signal, and the inverted data strobe signal. Rising edge data is latched into the memory in response to the first strobe signal and falling edge data is latched into the memory in response to the second strobe signal.