Joo H Kim

US Patent:

7718500, May 18, 2010

Filed:

Dec 16, 2005

Appl. No.:

11/305584

Inventors:

Yung Fu Chong - Singapore, SG
Zhijiong Luo - Carmel NY, US
Joo Chan Kim - Fishkill NY, US
Judson Robert Holt - Wappingers Falls NY, US

Assignee:

Chartered Semiconductor Manufacturing, Ltd - Singapore
International Business Machines Corporation (IBM) - Armonk NY
Samsung Electronics Co., Ltd. - Suwon-si, Gyeonggi-do

International Classification:

H01L 21/336

US Classification:

438300, 438233, 438509, 257E2143, 257E21431, 257E21631

Abstract:

A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

US Patent:

7939413, May 10, 2011

Filed:

Dec 8, 2005

Appl. No.:

11/297522

Inventors:

Yung Fu Chong - Singapore, SG
Zhijiong Luo - Carmel NY, US
Joo Chan Kim - Fishkill NY, US
Brian Joseph Greene - Yorktown Heights NY, US
Kern Rim - Yorktown Heights NY, US

Assignee:

Samsung Electronics Co., Ltd.
Chartered Semiconductor Manufacturing, Ltd. - Singapore

International Classification:

H01L 21/336

US Classification:

438300, 438197, 438222, 438226, 257E21431

Abstract:

An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e. g. , SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

US Patent:

8288825, Oct 16, 2012

Filed:

May 17, 2010

Appl. No.:

12/780962

Inventors:

Yung Fu Chong - Singapore, SG
Zhijiong Luo - Carmel NY, US
Joo Chan Kim - Fishkill NY, US
Judson Robert Holt - Wappingers Falls NY, US

Assignee:

GLOBALFOUNDRIES Singapore Pte. Ltd. - Singapore

International Classification:

H01L 21/70

US Classification:

257369, 257616

Abstract:

A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.