Joo Y Park

US Patent:

6728140, Apr 27, 2004

Filed:

Dec 5, 2001

Appl. No.:

10/011157

Inventors:

Kyung Joon Han - Palo Alto CA
Joo Weon Park - Pleasanton CA
Dung Tran - San Jose CA
Steve K. Hsia - San Jose CA
Jong Seuk Lee - Palo Alto CA
Dae Hyun Kim - Fremont CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518524, 36518526, 3651853, 36518529

Abstract:

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

US Patent:

6768671, Jul 27, 2004

Filed:

Mar 5, 2003

Appl. No.:

10/382719

Inventors:

Joo Weon Park - Pleasanton CA
Kwangho Kim - Sunnyvale CA
Eungjoon Park - Fremont CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1616

US Classification:

36518502, 36518523, 36518512, 36518511, 36518533, 36518529

Abstract:

In an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.

US Patent:

6775184, Aug 10, 2004

Filed:

Jan 21, 2003

Appl. No.:

10/349384

Inventors:

Joo Weon Park - Pleasanton CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1400

US Classification:

36518508, 3651852, 36518522, 365154

Abstract:

A memory integrated circuit includes a nonvolatile memory array that is programmed in page mode. A volatile utility memory is connected to the memory array, and is at least a page in size so that an entire page of data that is either being programmed into or read from the memory array may be stored in the utility memory, thereby providing a single readily accessible and fully functional volatile memory that supports a variety of data operations such as nonvolatile memory programming, program-verify when supplemented with a program verify detector, data compare when supplemented with a comparator, and other operations including, in particular, operations that can benefit from the availability of a fast volatile memory to store an entire page of program data or read data. The outputs of the program verify detector, the comparator, and potentially the other operations circuits are furnished to a memory control circuit for controlling the memory or setting particular register values, or may be furnished as output through an I/O circuit that implements data input/output functions and performs various data routing and buffering functions for the integrated circuit memory.

US Patent:

6826080, Nov 30, 2004

Filed:

May 24, 2002

Appl. No.:

10/154979

Inventors:

Joo Weon Park - Pleasanton CA
Kyung Joon Han - Palo Alto CA
Jong Seuk Lee - Palo Alto CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518505, 36518511, 36518516, 36518533

Abstract:

In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

US Patent:

6873004, Mar 29, 2005

Filed:

Feb 4, 2003

Appl. No.:

10/358645

Inventors:

Kyung Joon Han - Palo Alto CA, US
Steve K. Hsia - San Jose CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Palo Alto CA, US

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

H01L029/788

US Classification:

257315, 257E293, 257 6, 438266, 438286, 438302, 438525

Abstract:

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

US Patent:

6909639, Jun 21, 2005

Filed:

Apr 22, 2003

Appl. No.:

10/421458

Inventors:

Joo Weon Park - Pleasanton CA, US
Eungjoon Park - Fremont CA, US
Kyung Joon Han - Palo Alto CA, US

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C016/00

US Classification:

36518525, 365204

Abstract:

The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.

US Patent:

7558900, Jul 7, 2009

Filed:

Mar 11, 2005

Appl. No.:

11/078205

Inventors:

Robin J. Jigour - San Jose CA, US
Eungjoon Park - Fremont CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Palo Alto CA, US

Assignee:

Winbound Electronics Corporation - Hisn Chu

International Classification:

G06F 13/14
G06F 3/00
G06F 13/42

US Classification:

710305, 710 11, 710105

Abstract:

A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

US Patent:

20100049948, Feb 25, 2010

Filed:

Jul 2, 2009

Appl. No.:

12/459590

Inventors:

Robin J. Jigour - San Jose CA, US
Eungjoon Park - Fremont CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Pal Alto CA, US

Assignee:

Winbond Electronics Corporation - Hisn Chu

International Classification:

G06F 9/30
G06F 12/00
G06F 12/02

US Classification:

712208, 711103, 711E12001, 712E0903

Abstract:

A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.