Jose S Nunez

US Patent:

6338121, Jan 8, 2002

Filed:

May 20, 1999

Appl. No.:

09/315539

Inventors:

Jose Melanio Nunez - Austin TX
Thomas Albert Petersen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711140, 711150

Abstract:

A multiprocessor computer system including a set of processors connected to a memory subsystem via a local interconnect. The memory subsystem includes a load miss block suitable for queuing a first processor load operation that misses in an L1 cache of the first processor and a store miss block suitable for queuing store type operations. The subsystem further includes an arbiter suitable for receiving queued operations from the load and store miss blocks. The arbiter is further configured for selecting one of the received operations and initiating the selected operation. The subsystem further includes means for snooping the address associated with the first processor load operation when the first processor load operation is selected and initiated by the arbiter. The subsystem further includes a snoop control block adapted to receive a snoop response from a second processor associated with the memory subsystem. The snoop control block is further adapted to queue a store type operation in the store miss block if the snoop response from the second processor is modified.

US Patent:

6389516, May 14, 2002

Filed:

May 20, 1999

Appl. No.:

09/315542

Inventors:

Jose Melanio Nunez - Austin TX
Robert Podnar - Austin TX
Marie Jeannette Sullivan - Leander TX

Assignee:

International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1208

US Classification:

711146

Abstract:

A computer system including a first multiprocessor system connected to a system bus and adapted to forward first and second load requests to the system bus where the first load request precedes the second load request. The system further includes a second multiprocessor system connected to the system bus. The second multiprocessor system includes a memory subsystem comprised of first and second cache levels arranged such that an operation that retrieves data from the first cache level is arbitrated through the second cache level before the data becomes available to the system bus. A snoop control state machine of the second multiprocessor system is adapted to stall arbitration of a second operation initiated in the second cache level responsive to the second load request until a first operation initiated in the first cache level responsive to the first load request has been arbitrated through the second cache level. In other words, new operations to a lower cache level are stalled until older operations pass the common arbitration point. The second multiprocessor is preferably adapted to send a data ready signal to the first multiprocessor when data associated with the first load request is available for transmission over the system bus.

US Patent:

6430658, Aug 6, 2002

Filed:

May 20, 1999

Appl. No.:

09/315540

Inventors:

Jose Melanio Nunez - Austin TX
Thomas Albert Petersen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711146, 711124

Abstract:

A multi processor computer system including a set of processors connected to a memory subsystem via a local interconnect. The memory subsystem includes a load miss block suitable for queuing a first processor load operation that misses in an L cache of the first processor and a store miss block suitable for queuing store type operations. The subsystem further includes an arbiter suitable for receiving queued operations from the load and store miss blocks. The arbiter is further configured for selecting one of the received operations and initiating the selected operation. The subsystem further includes means for snooping the address associated with the first processor load operation when the first processor load operation is selected and initiated by the arbiter. The subsystem further includes a snoop control block adapted to receive a snoop response from a second processor associated with the memory subsystem. The snoop control block is further adapted to queue a store type operation in the store miss block if the snoop response from the second processor is modified.

US Patent:

6460133, Oct 1, 2002

Filed:

May 20, 1999

Appl. No.:

09/315488

Inventors:

Jose Melanio Nunez - Austin TX
Thomas Albert Petersen - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

712214

Abstract:

A multiprocessor computer system including a set of processors where each processor in the set includes an execution unit for issuing operations and a processor queue suitable for queuing previously issued and still pending operations. The multiprocessor further includes means for forwarding operations issued by the processor to the processor queue and to an operation block queue of a memory subsystem that is connected to the multiprocessor. The depth of (i. e. , the number of entries in) the operation block queue matches the depth of the processor queue. The processor queue, when full, inhibits the processor from issuing additional operations. In this manner, an operation issued by the processor is guaranteed an available entry in the operation block queue of the memory subsystem thereby eliminating the need for operation retry circuitry and protocols such as handshaking. Preferably, each processor queue includes a processor load queue and a processor store queue and the operation block queue includes a load queue and a store queue. In this embodiment, the depth of each of the processor load and store queues matches the depth of the operation block load and store queues respectively.

US Patent:

6615323, Sep 2, 2003

Filed:

Sep 2, 1999

Appl. No.:

09/389445

Inventors:

Thomas Albert Petersen - Austin TX 78759
Jose Melanio Nunez - Austin TX 78727
Marie Jeannette Sullivan - Leander TX 78641

International Classification:

G06F 1342

US Classification:

711146

Abstract:

A system and method are provided for maintaining cache coherency in symmetric multiprocessor system by having logic for performing snoop queries separate from logic for performing snoop actions. This logic split permits increased throughput because pending snoop queries must no longer wait until snoop actions complete. Two state machines are disclosed: a pipeline state machine for snoop queries; and a snoop action state machine, for executing the split logic handling snoop requests.

US Patent:

6847990, Jan 25, 2005

Filed:

May 17, 2002

Appl. No.:

10/150671

Inventors:

Srinath Audityan - Austin TX, US
Marie J. Sullivan - Leander TX, US
Jose M. Nunez - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 1328

US Classification:

709212

Abstract:

A data transfer unit is able to read data from a source at the source coherency granule size and write data at the destination coherency granule size even though the two granule sizes may be different. A data transfer unit has registers for storing the granule size information in preparation of performing a transfer of a data block between a source and a destination. The data block is transferred in sub-blocks. Except for the first and last sub-blocks, the sub-blocks, for a read, are sized to the source coherency granule size, which is the transfer size that has been optimized for the source. For the write, the sub-blocks are sized to the destination coherency granule size, which is the transfer size that has been optimized for the destination. Thus, both the read and the write are optimized even though the transfers themselves are among devices with different coherency granules.

US Patent:

6898682, May 24, 2005

Filed:

Aug 12, 2002

Appl. No.:

10/217174

Inventors:

James A. Welker - Austin TX, US
Srinath Audityan - Austin TX, US
Jose M. Nunez - Austin TX, US
Robert C. Podnar - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F012/00

US Classification:

711163, 365233

Abstract:

In response to a clock cycle and a pending READ command for data with a variably recurring access latency, a clock cycle count is adjusted. If a latency value has not been locked and if the READ command is a first READ command, the clock cycle count is stored as a locked latency value upon receiving a synchronized data available event (DQS for instance). Each subsequent READ command has an associated clock cycle count to enable pipelining wherein the clock cycle count for each READ starts incrementing when the individual READ command is issued. For subsequent READ commands, if the cycle count compares favorably with the locked latency value, data can be sampled safely from the interface at the identical latency for every READ request issued. The locked latency value can be read and/or written by software/hardware such that the read latency is consistent across multiple devices for reproducibility during debug.

US Patent:

6937961, Aug 30, 2005

Filed:

Sep 26, 2002

Appl. No.:

10/255427

Inventors:

Carlos J. Cabral - Austin TX, US
Jose M. Nunez - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F015/00

US Classification:

702182, 709226

Abstract:

Embodiments of the present invention relate generally to a monitoring unit and method which counts a number of qualified clusters of a selected event type based on a size threshold, granularity threshold, and distance threshold time. In one embodiment, a qualified cluster is a cluster which meets both the size threshold and granularity threshold. In one embodiment, a qualified cluster is detected and counted by the cluster counter if it occurs at least the distance threshold time after a previous counted qualified cluster. For example, in one implementation, the performance monitor waits until a distance threshold time expires prior to detecting a next qualified cluster. Alternatively, all qualified clusters are detected where the cluster counter counts a qualified cluster only if it occurs at least the distance threshold time after a previous qualified cluster, regardless of whether it was counted by the cluster counter or not.