Joseph F Chan

US Patent:

53428056, Aug 30, 1994

Filed:

Jul 1, 1993

Appl. No.:

8/082951

Inventors:

Joseph Y. Chan - Kings Park NY
Larry Laterza - Miller Place NY
Dennis Garbis - Huntington Station NY
William G. Einthoven - Belle Mead NJ

Assignee:

G.I. Corporation - Hatboro PA

International Classification:

H01L 2120

US Classification:

117 89

Abstract:

This invention concerns itself with an improved method of producing sharply defined misfit dislocations; (MD) with a new, inexpensive method of doping these misfit dislocations with Au; with invention that a combination of Au and Pt doping in misfit dislocations is superior to any amount of Au and to some specific placements of the misfit dislocations in the device structure.

US Patent:

58829865, Mar 16, 1999

Filed:

Mar 30, 1998

Appl. No.:

/050106

Inventors:

Jack Eng - Bellmore NY
Joseph Y. Chan - Kings Park NY
Willem G. Einthoven - Somerset NJ
John E. Amato - Taipei, TW
Sandy Tan - Farmingdale NY
Lawrence LaTerza - Miller Pl. NY
Gregory Zakaluk - Seaford NY
Dennis Garbis - South Huntington NY

Assignee:

General Semiconductor, Inc. - Melville NY

International Classification:

H01L 2130
H01L 2146

US Classification:

438456

Abstract:

Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

US Patent:

56354142, Jun 3, 1997

Filed:

Mar 28, 1995

Appl. No.:

8/409762

Inventors:

Gregory Zakaluk - Seaford NY
Dennis Garbis - S. Huntington NY
Willem Einthoven - Belle Mead NJ
Joseph Chan - Kings Park NY
Jack Eng - Bellmore NY
Jun Wu - Coram NY
John Amato - Northport NY

International Classification:

H01L 21265

US Classification:

438471

Abstract:

Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

US Patent:

53605098, Nov 1, 1994

Filed:

Mar 8, 1993

Appl. No.:

8/021130

Inventors:

Gregory Zakaluk - Seaford NY
Dennis Garbis - Huntington Station NY
Joseph Y. Chan - Kings Park NY
John Latza - Lindenhurst NY
Lawrence LaTerza - Miller Place NY

Assignee:

GI Corporation - Hatboro PA

International Classification:

H01L 21306

US Classification:

156645

Abstract:

Significant reductions in the cost of fabrication of epitaxial semiconductor devices without sacrifice of functional characteristics is achieved by eliminating the conventional but costly polishing procedure, instead subjecting the substrate to grinding, cleaning and etching processes in which the grinding removes material from the surface to a depth of at least 65 microns and the etching further removes material to a depth of about 6-10 microns, the grinding preferably being carried out in two steps, the first being a coarse step and the second being a fine step, with the rotated grinding elements dwelling at their respective last grinding positions for a short period of time. The result is the equivalent of the prior art polishing procedure which took considerably longer to carry out and which therefore was much more costly. Complementing this grinding procedure is an improved and cost effective epitaxial process utilizing a unique two-step hydrochloric gas high temperature etch and a faster growth rate process with shorter cycle steps. In addition, oxygen control and "gettering" capabilities result in a total process improving the economics of formation of epitaxial semiconductor devices.

US Patent:

45221499, Jun 11, 1985

Filed:

Nov 21, 1983

Appl. No.:

6/553962

Inventors:

Dennis Garbis - Dix Hills NY
Joseph Y. Chan - Kings Park NY
Amedeo J. Granata - Flushing NY
Robert C. Heller - Stony Brook NY

Assignee:

General Instrument Corp. - Clifton NJ

International Classification:

C23C 1308

US Classification:

118725

Abstract:

A reactor for use in a chemical vapor deposition process occurring in a radiant absorption heater system employs a vertical gas flow reaction vessel and a novel substantially solid susceptor configured as a truncated wedge. The susceptor is characterized by a high utilized area, resulting in a high wafer capacity and low power requirement.

US Patent:

46594000, Apr 21, 1987

Filed:

Jun 27, 1985

Appl. No.:

6/750488

Inventors:

Danny Garbis - South Huntington NY
Joseph J. Chan - Kings Park NY
Amadeo J. Granata - Mount Vernon NY
Philip Coniglione - Glen Cove NY
Thomas D. Briglia - Hauppauge NY
Lawrence E. Laterza - Coram NY

Assignee:

General Instrument Corp. - New York NY

International Classification:

H01L 736
H01L 2120

US Classification:

148175

Abstract:

A silicon substrate having a controlled oxygen content is sliced to form a wafer. The backside surface of the wafer is mechanically damaged for external gettering, polished, and subjected to heat for annealing to reduce strain and defects near the surface. The surface is then etched and the epitaxial layer formed by first growing an epitaxial layer, removing a substantial portion thereof, and then regrowing the layer to the required thickness. Immediately prior to device processing, an oxide layer is formed by heating the wafer, removing a portion of the epitaxial layer, and placing the wafer in an oxygen atmosphere. After a preselected time period in the oxygen atmosphere, the temperature is gradually reduced.

US Patent:

54321212, Jul 11, 1995

Filed:

May 16, 1994

Appl. No.:

8/242877

Inventors:

Joseph Chan - Kings Park NY
Dennis Garbis - Huntington Station NY
Lawrence Laterza - Miller Pace NY
Gregory Zakaluk - North Seaford NY

Assignee:

GI Corporation - Hatboro PA

International Classification:

H01L 2120

US Classification:

437 95

Abstract:

An all epitaxial process performed entirely in a CVD reactor is employed to grow epitaxial layers with accurately controlled successively low and high dopant concentrations over a heavily doped substrate, eliminating the need for a separate diffusion, even for high purity concentrations. After purging the reactor system, the heavily doped silicon substrate is "capped" by growing two successive very thin silicon sublayers of the same conductivity type. The reactor chamber is subjected to a hydrogen purge to deplete any contaminents after each sublayer is formed. The cap sublayers form a narrow, abrupt intrinsic transition region with the substrate and become an active part of the device structure. A lightly doped epitaxial layer is grown over the "capped" substrate so that a depletion region can be formed in the device under suitable reverse bias. A heavily doped epitaxial layer is then grown over the lightly doped epitaxial layer.

US Patent:

55713297, Nov 5, 1996

Filed:

Mar 28, 1995

Appl. No.:

8/411408

Inventors:

Joseph Chan - Kings Park NY
Dennis Garbis - Huntington Station NY
John Sapio - Huntington NY
John Latza - Lindenhurst NY

Assignee:

GI Corporation - Hatsboroa PA

International Classification:

C23C 1600

US Classification:

118715

Abstract:

To minimize contamination of gas flow lines and reactor surfaces from high impurity concentrations present in the CVD reactor, control of the dopant gas supply is located closely adjacent to the reactor input port and the dopant gas supply line is separately vented. First and second dopant gas supplies and a diluent gas supply are connected to branch lines which converge to form the dopant supply line. A solenoid valve is situated in the main dopant supply line as close to the input port as possible. A vent line is connected to the dopant supply line, prior to the solenoid valve. The etchant and silicon gas supplies are each connected to the reactor input by a separate supply line. The etchant and silicon gas supply lines are vented separately from the dopant gas supply line.