Joseph F Cicchiello

US Patent:

55923925, Jan 7, 1997

Filed:

Nov 22, 1994

Appl. No.:

8/343756

Inventors:

Thomas G. Matheson - Brookside NJ
Joseph F. Cicchiello - Phillipsburg NJ
Glenn Wikle - South Orange NJ

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 1500

US Classification:

364490

Abstract:

Method and apparatus for design integrated circuit layouts with extensible elements. The elements are generated by extensible element programs the first time the element is selected for a design, with the results stored in a run time cache. Element entries in the cache are accessible through a hash table, with each element reference hashed to provide a hash handle to the table. Subsequent hashes of an element reference provide access to the cache so that the same extensible element need not be regenerated by the element program each time the element is selected. To reduce the cache size, only the attributes of an element derived from the defining attributes of an element are cached. Other attributes such as location and orientation are stored with the element reference as part of a circuit design in a design database. In this way, related but different elements may use the same cache entry, with the differences then added once the cache entry is retrieved.