Joseph D Dunbar

US Patent:

53961110, Mar 7, 1995

Filed:

Mar 11, 1993

Appl. No.:

8/029457

Inventors:

Ralph C. Frangioso - Franklin MA
Paul Rebello - Northboro MA
Joseph M. Dunbar - Brookfield MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

H03K 513

US Classification:

327144

Abstract:

A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals. The use of such gated clock signal generation circuitry can reduce the time needed to generate the gated clock signals from that required by previously used register PAL circuitry to improve performance of the processing system.