Joseph P Farrell

US Patent:

51828006, Jan 26, 1993

Filed:

Nov 16, 1990

Appl. No.:

7/614524

Inventors:

Joseph K. Farrell - Boca Raton FL
Jeffrey S. Gordon - Centreville VA
Daniel C. Kuhl - Delray Beach FL
Timothy V. Lee - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

395425

Abstract:

An improved multi-channel direct memory access (DMA) controller for data processing systems provides adaptive pipelining and time overlapping of operations performed relative to communication channels. Registers and resources used to pipeline communication data and control signals relative to plural channels are adaptively shared relative to a single channel when command chaining is required relative to that channel. In command chaining a plural word command, termed a Device Control Block (DCB), is fetched from an external system memory via a bus having severe time constraints relative to potential real time requirements of the channels. Pipelining and time overlapping of channel operations, relative to plural channels, increases the effective rate of transfer at the bus interface to the system memory, and thereby allows for the controller to be used for applications in which throughput requirements and bus access constraints could otherwise conflict.

US Patent:

55308945, Jun 25, 1996

Filed:

May 2, 1995

Appl. No.:

8/432999

Inventors:

Joseph K. Farrell - Boca Raton FL
Jeffrey S. Gordon - Centreville VA
Robert V. Jenness - Boca Raton FL
Daniel C. Kuhl - Delray Beach FL
Timothy V. Lee - Boca Raton FL
Tony E. Parker - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395800

Abstract:

Disclosed is an arrangement for "seamlessly" integrating telephone services relative to primitive analog telephone equipment into general purpose computer systems. The integration is effected through present "secondary" adaptation of data link control adapter devices which are adapted primarily for coupling such computer systems to high speed data communication links for transmission and reception of digital data. This permits general resources of the computer system (keyboard, memory, disk drives, etc. ) to be used for specific applications associated with telephone services. Presently described link control devices have a telephone attachment port which couples through analog-to-digital conversion circuits to a primitive analog telephone (no dial or keys). Such devices operate normally in time division multiplex to process communication data between a computer (host) system and data link ports. The present adaptation includes a host programmable time division switch circuit within the control device, which can be conditioned dynamically to route digitized telephone signals directly between its data link and telephone ports, whereby telephone signals can be transmitted isochronally between a local user of the host system and a remote telephone, over a telephone network connection, while data signals are being transferred in either direction between the host system and equipment at the remote telephone station over the same connection.

US Patent:

51213907, Jun 9, 1992

Filed:

Mar 15, 1990

Appl. No.:

7/495810

Inventors:

Joseph K. Farrell - Boca Raton FL
Jeffrey S. Gordon - Centreville VA
Robert V. Jenness - Boca Raton FL
Daniel C. Kuhl - Delray Beach FL
Timothy V. Lee - Boca Raton FL
Tony E. Parker - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 324

US Classification:

370 941

Abstract:

A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e. g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces.

US Patent:

52069338, Apr 27, 1993

Filed:

Mar 15, 1990

Appl. No.:

7/495821

Inventors:

Joseph K. Farrell - Boca Raton FL
Jeffrey S. Gordon - Centreville VA
Daniel C. Kuhl - Delray Beach FL
Timothy V. Lee - Boca Raton FL
Tony E. Parker - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 700

US Classification:

395200

Abstract:

An integrated data link control device (IDLC) interfaces between a host computer system and external channels in a communication network. The device contains multiple internal channels allocatable individually to interface to the external channels, each internal channel having internal buffer memory reserved to it for storing data signals handled by it. The device also includes facilities for selectively configuring groups of its internal channels into "extended channels", some of which are termed Hyper Channels. Channels in each extended channel group interface collectively and in time coordination to one external channel, presenting an effective bandwidth to the external channel which is greater than the bandwidth of any single internal channel. One channel in each group is designated as a reference channel for the group, and all data signals transferred between the group and the assigned external channel are funneled through only the buffer memory assigned to the respective reference channel; in order to ensure that such signals are transferred between the external channel and the host system in their correct "message" sequence.

US Patent:

52186806, Jun 8, 1993

Filed:

Mar 15, 1990

Appl. No.:

7/495232

Inventors:

Joseph K. Farrell - Boca Raton FL
Jeffrey S. Gordon - Centreville VA
Daniel C. Kuhl - Delray Beach FL
Timothy V. Lee - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300
G06F 1516
H04J 304

US Classification:

395325

Abstract:

A "single-chip" integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes.

US Patent:

52415414, Aug 31, 1993

Filed:

Mar 15, 1990

Appl. No.:

7/495012

Inventors:

Joseph K. Farrell - Boca Raton FL
Jeffrey S. Gordon - Centreville VA
Daniel C. Kuhl - Delray Beach FL
Timothy V. Lee - Boca Raton FL
Tony E. Parker - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 324

US Classification:

370 941

Abstract:

Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot.

US Patent:

20080056823, Mar 6, 2008

Filed:

Sep 18, 2007

Appl. No.:

11/856792

Inventors:

Joseph Farrell - Ft. Lauderdale FL, US

International Classification:

E02B 3/04
B63B 22/08

US Classification:

405023000, 441002000

Abstract:

A beach erosion abatement system includes positioning a primary shoal module proximately to a low tide water point and submersed in a depth of water to conceal a top portion of the shoal module. The shoal module includes a hollow internal compartment, a water access port in fluid communication with the internal compartment and an air access port in fluid communication with the internal compartment. A water pump is connected to the water access port and water is pumped into the internal compartment of the shoal module to flood or sink the shoal module. The shoal module may be refloated by coupling an air pump to the air access port and pumping air into the internal compartment of the shoal module to force the water out of the water access port. Further, the water may be pumped out of the internal compartment while air is vented into the internal compartment.