Joseph D Hall

US Patent:

42518342, Feb 17, 1981

Filed:

May 29, 1979

Appl. No.:

6/042749

Inventors:

Joseph E. Hall - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 314

US Classification:

358213

Abstract:

A charge-coupled device (CCD) imager has an output shift register having a number of bits equal to at least a multiple (N), where N is an integer greater than 1, times the number of columns of pixels in the imager. Appropriately spaced in the output shift register are N groups of N outputs each for non-destructive, simultaneous readout of N. times. N bits. The N. times. N bits are then available for pre-processing or display without the requirement for having previously stored each bit, digitally represented, in a computer memory.

US Patent:

43694683, Jan 18, 1983

Filed:

Nov 10, 1980

Appl. No.:

6/205856

Inventors:

Joseph E. Hall - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 314

US Classification:

358213

Abstract:

A charge-coupled device (CCD) imager has an output shift register having a number of bits equal to at least a multiple (N), where N is an integer greater than 1, times the number of columns of pixels in the imager. Appropriately spaced in the output shift register are N groups of N outputs each for non-destructive, simultaneous readout of N. times. N bits. The N. times. N bits are then available for pre-processing or display without the requirement for having previously stored each bit, digitally represented, in a computer memory.

US Patent:

45382875, Aug 27, 1985

Filed:

Jun 4, 1979

Appl. No.:

6/045466

Inventors:

Charles G. Roberts - Plano TX
Joseph E. Hall - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1928
H01L 2978

US Classification:

377 60

Abstract:

A floating gate amplifier in a charge-coupled device (CCD) permitting non-destructive readout, where the floating gate is conductively coupled through a high resistance element to a bias voltage. The floating gate is defined by a lower level of metallization which is embedded in an insulating layer and crosses the charge transfer channel. In one embodiment the floating gate is connected to the source of a metal-oxide-semiconductor transistor and the drain of the transistor is connected to an upper level conductor which is a bias line. In another embodiment, the anode of a diode is connected to the floating gate and the diode cathode is connected to the bias line. A pair of control gates adjacent to and partially overlapping the floating gate transfer charge packets and improve sensitivity. Reading is accomplished by detecting voltages induced on the floating gate by the charge packets.