Joseph D Marino

US Patent:

20030115515, Jun 19, 2003

Filed:

Dec 13, 2001

Appl. No.:

10/022463

Inventors:

Chris Curtis - Scottsdale AZ, US
Joseph Marino - Prescott AZ, US
Bruce Fette - Mesa AZ, US

International Classification:

G01R031/28

US Classification:

714/712000

Abstract:

In a digital channel of a digital wireless communication system including at least one mobile station, at least one base transceiver station in communication with the mobile station, a transcoder configured to provide a signal conversion between vocoder frames and pulse code modulation, and a mobile switching center for interconnecting the digital wireless communication system to a public switched telephone network, a method and apparatus for determining a fault in the digital channel is disclosed. The method includes generating a first set of vocoder input parameters from a speech input signal, and generating a second set of vocoder input parameters from an output signal substantially equivalent to the speech input signal as it is received at a mobile station via the digital channel. The method further includes calculating a metric based on the first and the second set of vocoder input parameters, and subsequently determining a fault in the digital channel using the metric.

US Patent:

49875957, Jan 22, 1991

Filed:

Sep 11, 1989

Appl. No.:

7/405157

Inventors:

Joseph T. Marino - Fountain Hills AZ
Ronald S. Core - Glendale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 902

US Classification:

380 50

Abstract:

A secure processor arrangement for a communications secure kernel of a secure processor system. This processor arrangement provides protection of plain text data and suitable isolation of data necessary to support single processor architecture. A red memory subsystem stores plain text data and a black memory subsystem stores cypher text data. In order to prevent mishandling of plain text data, the single processor is allowed to directly read and to write red memory, but the single processor is only permitted to directly read from the black memory.

US Patent:

55307582, Jun 25, 1996

Filed:

Jun 3, 1994

Appl. No.:

8/253993

Inventors:

Joseph T. Marino - Fountain Hills AZ
Ernest W. Borgoyne - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 900

US Classification:

380 49

Abstract:

A computer network (20) including secure nodes (26) and unsecured nodes (28). The secure nodes (26) may communicate private data without compromising security provisions. The secure nodes (26) include a security kernel (36) that implements communication security provisions and a trusted operating system (40) that imposes computer data security provisions. A trusted interface (44) is used to transfer data between the trusted operating system (40) and the security kernel (36). In addition, this interface (44) insures that computer security attributes are compatible with communication security attributes. If incompatibilities are discovered, requested communications are thwarted and audit records for the security linkage violations are recorded.

US Patent:

42740851, Jun 16, 1981

Filed:

Jun 28, 1979

Appl. No.:

6/053018

Inventors:

Joseph T. Marino - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 504

US Classification:

340347DD

Abstract:

A DES (Data Encryption Standard) system utilizing an input register, control logic and output register to provide for a selection from a multiplicity of operable modes on a single chip or family of chips.

US Patent:

42623588, Apr 14, 1981

Filed:

Jun 28, 1979

Appl. No.:

6/053019

Inventors:

Joseph T. Marino - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1110

US Classification:

371 51

Abstract:

A system for providing on-line parity checking in data encryption/decryption systems such as DES and which is especially useful where multiple stage shifting is accomplished on a single clock input to the algorithm shift register of such a system. The parity system provides for simultaneous parity checks on a plurality of bytes where the bits of each byte are distributed through the algorithm shift register in a pseudorandom pattern.

US Patent:

45876258, May 6, 1986

Filed:

Jul 5, 1983

Appl. No.:

6/510717

Inventors:

Joseph T. Marino - Chandler AZ
Ronald V. Chandos - Tempe AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

G06F 1516
G06F 1560

US Classification:

364578

Abstract:

A hardware simulator for simulating digital structures includes a general purpose computer and an improved simulator processor. The improved processor handles an advanced primitive having four inputs and one output and which is capable of representing a memory cell or similar structure. The architecture of the processor provides highly efficient compilation of the input states of a primitive and the primitive evaluator and resolver logic provide the output state in a minimum number of clock cycles. The simulator is a single, low cost unit capable of simulating 64K cell structures with a speed comparable to prior art simulators.

US Patent:

48211737, Apr 11, 1989

Filed:

Mar 7, 1988

Appl. No.:

7/168577

Inventors:

Ronald J. Young - Mesa AZ
Ronald S. Core - Glendale AZ
Joseph T. Marino - Fountain Hills AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1520
G06F 1574
G06F 7544
G06F 944

US Classification:

364200

Abstract:

The present invention consists of a hardware simulator with bus evaluator logic for use in simulating and fault grading of very large scale digital circuits containing buses. In this invention the status of a bus is continously upgraded each time a primitive is evaluated that has an output coupled to the bus. As bus driver primitives are evaluated, the state of the bus is determined on the fly and stored in an accumulator register, called the bus register. Evaluation of the bus continues using the data stored in the bus register and the state of each driver until all drivers have been evaluated. After the last bus driver is evaluated the state of the bus is known and the bus primitive is assigned the value, or state, stored in the bus register hardware and is passed to all receivers on the bus.

US Patent:

20190301712, Oct 3, 2019

Filed:

Jun 17, 2019

Appl. No.:

16/442820

Inventors:

Nicole Bagozzi - Mesa AZ, US
Scott Evans - Mesa AZ, US
Nicholas Garthright - Chandler AZ, US
Joseph Marino - Chandler AZ, US
Lee Marino - Gilbert AZ, US

International Classification:

F21V 21/02
G08B 5/36
F21V 33/00
H05B 37/02

Abstract:

Systems for emergency exit LED lighting are described herein. The emergency exit lighting systems comprise structures for housing at least one LED light, an LED driver electronically coupled to the LED light(s), a continuous power source, a backup power source, and a test switch. The fixtures, in various configurations, may be mounted to an existing T-grid or to a wall or ceiling. The fixture may be tested remotely.