Joseph R Michael

US Patent:

20150269090, Sep 24, 2015

Filed:

Jun 2, 2015

Appl. No.:

14/728541

Inventors:

- Dallas TX, US
Raguram Damodaran - Raleigh NC, US
Abhijeet Ashok Chachad - Plano TX, US
Joseph Raymond Michael Zbiciak - Farmers Branch TX, US

International Classification:

G06F 12/10
G06F 12/08

Abstract:

This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.