Joseph R Michael

US Patent:

6900707, May 31, 2005

Filed:

Nov 30, 2001

Appl. No.:

10/000744

Inventors:

Hernan Erlig - Thousand Oaks CA, US
Harold R. Fetterman - Santa Monica CA, US
Joseph Michael - Los Angeles CA, US

Assignee:

Pacific Wave Industries, Inc. - Los Angeles CA

International Classification:

H01P001/18

US Classification:

333156, 385 3, 385 8, 385 9, 359237, 359238

Abstract:

A power balanced photonic RF phase shifter includes: a microwave drive; a phase controller operably connected to the microwave drive; and a linearizing arm connected in parallel with the microwave drive, the linearizing arm operating under a bias voltage, V, that is controlled such that power variations of the photonic RF phase shifter are mitigated. In a preferred embodiment, the bias voltage, V, is controlled to keep an optical phase of the photonic RF phase shifter at a constant value. In a preferred embodiment, the microwave drive, the phase controller and the linearizing arm comprise (three) Mach-Zehnder modulators.

US Patent:

20220283809, Sep 8, 2022

Filed:

May 19, 2022

Appl. No.:

17/748954

Inventors:

- Dallas TX, US
Joseph Raymond Michael Zbiciak - San Jose CA, US

International Classification:

G06F 9/30
G06F 9/345
G06F 11/10
G06F 9/32
G06F 9/38
G06F 12/0875
G06F 12/0897
G06F 11/00

Abstract:

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

US Patent:

20230084716, Mar 16, 2023

Filed:

Nov 21, 2022

Appl. No.:

17/990812

Inventors:

- Dallas TX, US
Joseph Raymond Michael Zbiciak - Alviso CA, US

International Classification:

G06F 12/1045
G06F 9/30
G06F 9/345
G06F 9/38
G06F 11/00
G06F 11/10
G06F 7/24
G06F 7/487
G06F 7/499
G06F 7/53
G06F 7/57
G06F 9/48
G06F 17/16
H03H 17/06
G06F 9/32
G06F 12/0875
G06F 12/0897
G06F 12/0862
G06F 12/1009

Abstract:

In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

US Patent:

20210109868, Apr 15, 2021

Filed:

Oct 12, 2020

Appl. No.:

17/068730

Inventors:

- Dallas TX, US
Joseph Raymond Michael ZBICIAK - San Jose CA, US
Kai CHIRCA - Dallas TX, US
Daniel Brad WU - Plano TX, US

International Classification:

G06F 12/1027
G06F 12/1009
G06F 12/0882
G06F 12/0891

Abstract:

A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

US Patent:

20200356493, Nov 12, 2020

Filed:

Aug 26, 2019

Appl. No.:

16/551452

Inventors:

- Mountain View CA, US
Prashant Chandra - San Jose CA, US
David Alan Dillow - San Jose CA, US
Joseph Raymond Michael Zbiciak - San Jose CA, US
Horacio Andres Lagar Cavilla - Mountain View CA, US

International Classification:

G06F 12/1081
G06F 12/1009
G06F 11/30
G06F 12/109
G06F 9/455

Abstract:

Systems and methods of tracking page state changes are provided. An input/output is communicatively coupled to a host having a memory. The I/O device receives a command from the host to monitor page state changes in a region of the memory allocated to a process. The I/O device, bypassing a CPU of the host, modifies data stored in the region based on a request, for example, received from a client device via a computer network. The I/O device records the modification to a bitmap by setting a bit in the bitmap that corresponds to a location of the data in the memory. The I/O device transfers contents of the bitmap to the CPU, wherein the CPU completes the live migration by copying sections of the first region indicated by the bitmap to a second region of memory. In some implementations, the process can be a virtual machine, a user space application, or a container.

US Patent:

20200326941, Oct 15, 2020

Filed:

Apr 29, 2020

Appl. No.:

16/861347

Inventors:

- Dallas TX, US
Joseph Raymond Michael Zbiciak - San Jose CA, US

International Classification:

G06F 9/30
G06F 9/345
G06F 11/10
G06F 9/32
G06F 9/38
G06F 12/0875
G06F 12/0897
G06F 11/00

Abstract:

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

US Patent:

20190187985, Jun 20, 2019

Filed:

Feb 22, 2019

Appl. No.:

16/282508

Inventors:

- Dallas TX, US
Joseph Raymond Michael Zbiciak - Alviso CA, US

International Classification:

G06F 9/30
G06F 9/345
G06F 9/38
G06F 11/10
G06F 9/32
G06F 12/0875
G06F 12/0897
G06F 11/00

Abstract:

Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors. Local storage on the streaming engine is organized as sectors based on the number of rows in the matrix to allow overlapping transposition processing and to minimize memory accesses.

US Patent:

20190187986, Jun 20, 2019

Filed:

Feb 22, 2019

Appl. No.:

16/282526

Inventors:

- Dallas TX, US
Joseph Raymond Michael Zbiciak - Alviso CA, US

International Classification:

G06F 9/30
G06F 9/345
G06F 9/38
G06F 11/10
G06F 9/32
G06F 12/0875
G06F 12/0897
G06F 11/00

Abstract:

Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors.