Joseph M Michael

Address:

2949 Housley Dr, Dallas, TX 75228

Phone:

(972)2790941

VIN:

1HGCP3F81AA019290

Make:

HONDA

Model:

ACCORD

Year:

2010

US Patent:

8560896, Oct 15, 2013

Filed:

Sep 26, 2011

Appl. No.:

13/245164

Inventors:

Joseph Raymond Michael Zbiciak - Arlington TX, US
Raguram Damodaran - Plano TX, US
Abhijeet Ashok Chachad - Plano TX, US
Dheera Balasubramanian - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 11/00

US Classification:

714 54

Abstract:

This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.

US Patent:

8607000, Dec 10, 2013

Filed:

Sep 23, 2011

Appl. No.:

13/243411

Inventors:

Abhijeet Ashok Chachad - Plano TX, US
Roger Kyle Castille - Houston TX, US
Joseph Raymond Michael Zbiciak - Arlington TX, US
Dheera Balasubramanian - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/04
G06F 12/12

US Classification:

711129, 711133, 711E12043, 711E12046, 711E12069

Abstract:

This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.

US Patent:

20120191914, Jul 26, 2012

Filed:

Sep 26, 2011

Appl. No.:

13/245183

Inventors:

Jonathan (Son) Hung Tran - Murphy TX, US
Raguram Damodaran - Plano TX, US
Abhijeet Ashok Chachad - Plano TX, US
Joseph Raymond Michael Zbiciak - Arlington TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G06F 12/08

US Classification:

711122, 711E12024

Abstract:

This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

US Patent:

20120191916, Jul 26, 2012

Filed:

Sep 26, 2011

Appl. No.:

13/245206

Inventors:

Abhijeet Ashok Chachad - Plano TX, US
Roger Kyle Castille - Houston TX, US
Joseph Raymond Michael Zbiciak - Arlington TX, US
Dheera Balasubramanian - Richardson TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G06F 12/08

US Classification:

711122, 711E12024

Abstract:

A second level memory controller uses shadow tags to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.

US Patent:

20120192027, Jul 26, 2012

Filed:

Sep 23, 2011

Appl. No.:

13/243370

Inventors:

Jonathan (Son) Hung Tran - Murphy TX, US
Abhijeet Ashok Chachad - Plano TX, US
Joseph Raymond Michael Zbiciak - Arlington TX, US
Krishna Chaithanya Gurram - Allen TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H03M 13/05
G06F 11/10

US Classification:

714752, 714E11032

Abstract:

The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.

US Patent:

20120198166, Aug 2, 2012

Filed:

Sep 28, 2011

Appl. No.:

13/247260

Inventors:

Raguram Damodaran - Plano TX, US
Joseph Raymond Michael Zbiciak - Arlington TX, US
Naveen Bhoria - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 12/08

US Classification:

711122, 711E12024

Abstract:

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

US Patent:

20120290755, Nov 15, 2012

Filed:

Sep 12, 2011

Appl. No.:

13/230131

Inventors:

Abhijeet Ashok Chachad - Plano TX, US
Raguram Damodaran - Plano TX, US
Ramakrishnan Venkatasubramanian - Plano TX, US
Joseph Raymond Michael Zbiciak - Arlington TX, US

International Classification:

G06F 13/14

US Classification:

710244

Abstract:

A queuing requester for access to a memory system. Transaction requests received from two or more requestors access to the memory system. Each transaction request includes an associated priority value. A request queue is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system uses the selected priority value.

US Patent:

20220357952, Nov 10, 2022

Filed:

Jul 22, 2022

Appl. No.:

17/870926

Inventors:

- Dallas TX, US
Duc Quang Bui - Grand Prairie TX, US
Joseph Raymond Michael Zbiciak - San Jose CA, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

In one embodiment, a system includes a memory and a processor core. The processor core includes functional units and an instruction decode unit configured to determine whether an execute packet of instructions received by the processing core includes a first instruction that is designated for execution by a first functional unit of the functional units and a second instruction that is a condition code extension instruction that includes a plurality of sets of condition code bits, wherein each set of condition code bits corresponds to a different one of the functional units, and wherein the sets of condition code bits include a first set of condition code bits that corresponds to the first functional unit. When the execute packet includes the first and second instructions, the first functional unit is configured to execute the first instruction conditionally based upon the first set of condition code bits in the second instruction.