Joseph K Morrell

US Patent:

20040111687, Jun 10, 2004

Filed:

Dec 4, 2002

Appl. No.:

10/309654

Inventors:

Nagashyamala Dhanwada - Wappingers Falls NY, US
Glenn Holmes - Wappingers Falls NY, US
Joseph Morrell - Wappingers Falls NY, US
Jose Luis Correia Neves - Poughkeepsie NY, US
Natesan Venkateswaran - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/45
G06F017/50

US Classification:

716/008000

Abstract:

An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic, and achieves it without loss of accuracy in the results. Annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data. The floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner. The abstraction based approach phases out by abstracting the leaf level logic (thus reducing the solution space of the floorplanner) and reintroducing them in the form of floorplan constraints (to account for the presence of the leaf level logic while determining the location of large blocks). The abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner. The overall concept of driving a floorplanning algorithm with a path based hyper-edge representation also helps to provide structural information about the netlist to the floorplanner.