Joseph R Stevens

US Patent:

6993107, Jan 31, 2006

Filed:

Nov 28, 2001

Appl. No.:

09/996053

Inventors:

Stacy Jean Garvin - Curhan NC, US
Vernon Roberts Norman - Cary NC, US
Paul Alan Owczarski - Raleigh NC, US
Martin Leo Schmatz - Gallen, CH
Joseph Marsh Stevens - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03D 3/24

US Classification:

375376, 327156

Abstract:

A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.

US Patent:

7034566, Apr 25, 2006

Filed:

Feb 12, 2004

Appl. No.:

10/777952

Inventors:

Joseph M. Stevens - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 30, 326 21, 326 26, 326 27, 327108

Abstract:

Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.

US Patent:

7142624, Nov 28, 2006

Filed:

Sep 13, 2005

Appl. No.:

11/225600

Inventors:

Stacy Jean Garvin - Durham NC, US
Vernon Roberts Norman - Cary NC, US
Paul Alan Owczarski - Raleigh NC, US
Martin Leo Schmatz - Gallen, CH
Joseph Marsh Stevens - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03D 3/24

US Classification:

375376, 327156

Abstract:

The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

US Patent:

7332932, Feb 19, 2008

Filed:

May 4, 2006

Appl. No.:

11/417626

Inventors:

Hayden C. Cranford - Cary NC, US
Westerfield J. Ficken - Cary NC, US
David A. Freitas - Morgan Hill CA, US
Joseph M. Stevens - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16
H03K 19/003
H03K 19/0175

US Classification:

326 30, 326 21, 326 82, 326 95

Abstract:

A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

US Patent:

7893766, Feb 22, 2011

Filed:

Sep 10, 2009

Appl. No.:

12/557139

Inventors:

Todd Morgan Rasmus - Cary NC, US
Joseph Marsh Stevens - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 3/45

US Classification:

330258, 330261

Abstract:

A method and apparatus for extending the common mode range of a differential amplifier. A circuit has a common mode detection circuit, a common mode voltage inversion circuit, and a differential amplifier. The common mode detection circuit receives a differential signal and detects a common mode voltage. The common mode voltage inversion circuit is coupled to the common mode detection circuit. The common mode voltage inversion circuit has an input node that receives the common mode voltage and an output node that outputs body voltage, wherein the common mode voltage inversion circuit creates an inverse relationship between the common mode voltage and the body voltage. The differential amplifier includes a differential pair of transistors that have a pair of body terminals coupled to the output node of the common mode voltage inversion circuit.

US Patent:

7940846, May 10, 2011

Filed:

Jan 8, 2007

Appl. No.:

11/621016

Inventors:

Daniel P. Greenberg - Raleigh NC, US
Joseph M. Stevens - Durham NC, US
Westerfield J. Ficken - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 3/00

US Classification:

375257

Abstract:

A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

US Patent:

8363736, Jan 29, 2013

Filed:

Mar 10, 2011

Appl. No.:

13/044604

Inventors:

Hayden C. Cranford - Cary NC, US
Daniel P. Greenberg - Raleigh NC, US
Joseph M. Stevens - Morrisville NC, US
Westerfield J. Ficken - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 25/00
H04B 17/00

US Classification:

375257, 375224

Abstract:

A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.

US Patent:

20070159224, Jul 12, 2007

Filed:

Dec 21, 2005

Appl. No.:

11/314909

Inventors:

Amar Dwarka - Raleigh NC, US
Joseph Stevens - Morrisville NC, US

International Classification:

H03K 3/017

US Classification:

327175000

Abstract:

A completely differential approach to correcting duty-cycle distortions of a differential clock signal propagating through a differential amplifier. A duty-cycle distortion correction (DCDC) differential amplifier circuit/device is provided with a differential amplifier whose output wires are coupled to a correction circuit. The correction circuit comprises a differential low pass filter and a differential correction amplifier. The differential correction amplifier's output is dotted back into the output of the amplifier. The differential output of the amplifier is passed through the low pass filter, which provides differential DC output signals that triggers respective correction amplifier transistors to generate an inverted correction current that is added back to respective differential output pulse. The DCDC differential amplifier provides a completely differential approach to correction of duty-cycle distortions within the differential output.