Joshua E Caldwell

US Patent:

6969982, Nov 29, 2005

Filed:

Oct 3, 2003

Appl. No.:

10/678534

Inventors:

Joshua William Caldwell - Tucson AZ, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G05F003/16

US Classification:

323313, 323273, 323315

Abstract:

A circuit having a voltage regulated by a reference current. The circuit includes a current feedback loop and a reference current source that is capable of producing a reference current. The current feedback loop includes an output device, a voltage to current converter, and a current feedback element. The voltage to current converter is coupled to the output device. A node of the voltage to current converter is the regulated voltage. The current feedback element is coupled to the voltage to current converter to provide a feedback current from the voltage to current converter to compare with the reference current to produce an error signal that is input to a control terminal of the output device. Thus, the current feedback loop regulates the voltage at the node of the voltage to current converter.

US Patent:

6977491, Dec 20, 2005

Filed:

Oct 6, 2003

Appl. No.:

10/680500

Inventors:

Joshua William Caldwell - Tucson AZ, US
Steven Ashley Martinez - Tucson AZ, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G05F001/40

US Classification:

323282

Abstract:

A current limiting circuit. The current limiting circuit includes a device coupled to an output node of the current limiting circuit. The device is responsive to magnitude of a signal at the output node. Moreover, the device has a first mode and a second mode, depending on the magnitude of the signal. The current limiting circuit also has a regulation component that regulates a voltage at the output node when the device is in the first mode. The current limiting circuit also has an element having a current that limits current at the output node when the device is in the second mode.

US Patent:

7170352, Jan 30, 2007

Filed:

May 4, 2005

Appl. No.:

11/121785

Inventors:

Joshua William Caldwell - Tucson AZ, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03F 3/45

US Classification:

330261, 323273, 323274

Abstract:

A circuit for driving a capacitive load is provided. The circuit includes a differential signal sensor and a differential amplifier. The differential amplifier is arranged to drive the capacitive load. Further, the differential amplifier is arranged to receive an output voltage at one input, and to receive a reference voltage at another input. The output voltage is provided at the output of the differential amplifier. Also, the differential amplifier is arranged to receive a bias current. The differential signal sensor is arranged to determine whether the difference between the output voltage and the reference voltage is within a voltage window. If the difference between the output voltage and the reference voltage is inside of the voltage window, the bias current is provided at its normal value. However, if the difference between the output voltage and the reference voltage is outside of the voltage window, the bias current is increased so that the bias current linearly increases with respect to time.

US Patent:

6879194, Apr 12, 2005

Filed:

Aug 25, 2003

Appl. No.:

10/648530

Inventors:

Joshua William Caldwell - Tucson AZ, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L007/00

US Classification:

327143

Abstract:

An active power-on reset (POR) current comparator circuit creates a POR signal for resetting logic devices and masking reference startup signals during the initial power supply ramp of an integrated circuit. The comparator circuit provides a logic level signal (i. e. , the POR signal) that will actuate when a bias current is above a predetermined level as compared to another current. The predetermined level for the bias current is set by a ratio established between two resistance levels within the active POR current comparator circuit.