Judson A Lehman from Scottsdale, AZ, age 79

Us Patents

Block-Based Rotation Of Arbitrary-Shaped Images
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US Patent:

7376286, May 20, 2008
Filed:

Sep 18, 2002
Appl. No.:

10/245984
Inventors:

Kevin Locker - Scottsdale AZ, US
Judson Lehman - Scottsdale AZ, US
Assignee:

NXP B.V. - Eindhoven
International Classification:

G06K 9/32
G09G 5/00
US Classification:

382296, 345649
Abstract:

An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e. g. , to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.

System For Enhancing Fault Tolerance And Security Of A Computing System
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US Patent:

20030115503, Jun 19, 2003
Filed:

Dec 14, 2001
Appl. No.:

10/017569
Inventors:

Judson Lehman - Scottsdale AZ, US
Rajeev Sethia - Chandler AZ, US
Assignee:

Koninklijke Philips Electronics N.V.
International Classification:

G06F011/00
US Classification:

714/025000, 714/003000
Abstract:

A system for enhancing fault tolerances and security of a computing system having a system clock through monitoring the computing system for at least one of a series of security attacks and upon detection of security attacks, switching the system from the system clock to a secure clock.

Concurrent Serial Interconnect For Integrating Functional Blocks In An Integrated Circuit Device
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US Patent:

63178044, Nov 13, 2001
Filed:

Nov 30, 1998
Appl. No.:

9/201450
Inventors:

Paul S. Levy - Chandler AZ
Judson Alan Lehman - Scottsdale AZ
Assignee:

Philips Semiconductors Inc. - New York NY
International Classification:

G06F 1300
G06F 1314
US Classification:

710129
Abstract:

A circuit arrangement and method interface multiple functional blocks within an integrated circuit device via a concurrent serial interconnect capable of routing separate serial command, data and clock signals between functional blocks in the device. The concurrent serial interconnect utilizes a plurality of serial ports that are selectively coupled to one another by an interface controller to define one or more logical communication channels between two or more of the serial ports. Each serial port is coupled via a point-to-point interconnection with a port interface in a functional block. In addition, the concurrent serial interconnect facilitates the design of an integrated circuit device by supporting the addition of a serial interconnect to an assemblage of functional blocks, with each functional block associated with one of a plurality of serial ports in the serial interconnect.

Computing Device Having Semi-Dedicated High Speed Bus
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US Patent:

57178755, Feb 10, 1998
Filed:

Sep 22, 1995
Appl. No.:

8/532936
Inventors:

Huzefa H. Cutlerywala - Tempe AZ
Rajeev Jayavant - Phoenix AZ
Judson A. Lehman - Scottsdale AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1340
US Classification:

395308
Abstract:

An improved bus architecture is provided in which the bus connects a single master to multiple targets including one primary target. Bus usage is predominately between the master and one primary target at a very high data transfer rate. Traffic between the master and other secondary targets has a much lower bandwidth requirement. The bus uses a single frequency clock for transfers involving the primary target and transfers involving the secondary targets. In accordance with one embodiment of the invention, the master is connected to the primary high bandwidth target using a high speed protocol and separate read and write data paths which are always driven (i. e. , never tri-stated). Always driving the high speed data paths avoids the increased area and decreased performance that would be entailed by adding additional gating. The lower bandwidth targets are supported on a single bi-directional data path to minimize area.

Cache Memory Support In An Integrated Memory System
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US Patent:

54541077, Sep 26, 1995
Filed:

Nov 30, 1993
Appl. No.:

8/159186
Inventors:

Judson A. Lehman - Scottsdale AZ
Mike Nakahara - Phoenix AZ
Nicholas J. Richardson - Tempe AZ
Assignee:

VLSI Technologies - San Jose CA
International Classification:

G06F 1520
G06F 1300
US Classification:

395480
Abstract:

A low-cost, moderate performance small computer system is provided by allowing a single sharable block of memory to be independently accessible as graphics or main store memory. Allocation of the memory selected programmably, eliminating the need to have the maximum memory size for each block simultaneously. Performance penalties are minimized by dynamically allocating the memory bandwidth on demand rather than through fixed time slices. Efficient L2 cache memory support is provided based on a system controller having an integrated L2 cache controller and a graphics controller that supports an integrated memory system. The memory connected to the graphics controller may be partitioned into two sections, one for graphics and one for system use. Additionally, the system controller may or may not have attached additional memory for system use. L2 cache support is provided for all system memory, regardless of the controller that it is connected to.

Central Processing Unit Data Entering And Interrogating Device And Method Therefor
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US Patent:

55617611, Oct 1, 1996
Filed:

Sep 1, 1995
Appl. No.:

8/522856
Inventors:

Gary D. Hicok - Mesa AZ
Judson A. Lehman - Scottsdale AZ
Thomas Alexander - Hillsboro OR
Yong J. Lim - Seattle WA
David R. Evoy - Tempe AZ
Yongmin Kim - Seattle WA
Assignee:

YLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1100
US Classification:

39518306
Abstract:

A Central Processing Unit (CPU) debugging device and method therefor is disclosed which provides data entering and interrogating devices which will temporarily stop all CPU execution when desired by a user and allow a non-destructive intrusion into the contents of any of the CPU internal registers, state bits, and cache and local memories. After the desired CPU contents have been reviewed and subsequently altered or maintained by a user, the CPU execution may be resumed.

Method And Apparatus For Enhancing Access To A Shared Memory
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US Patent:

60088230, Dec 28, 1999
Filed:

Aug 1, 1995
Appl. No.:

8/510076
Inventors:

Desi Rhoden - Phoenix AZ
Judson Alan Lehman - Scottsdale AZ
Mike Nakahara - Kirkland WA
International Classification:

G06F 1316
US Classification:

345521
Abstract:

The present invention is directed to providing an organized memory which is accessed by multiple memory controllers while still exploiting the efficiencies which the organized memory was intended to provide. In accordance with exemplary embodiments, optimal efficiency in using the shared memory is achieved by buffering memory accesses which will not increase overhead during a memory write cycle. As a result, interruptions by one controller while another controller is accessing the shared memory are reduced to a minimum.

Caching Fifo And Method Therefor
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US Patent:

55577334, Sep 17, 1996
Filed:

Apr 2, 1993
Appl. No.:

8/042306
Inventors:

Gary D. Hicok - Mesa AZ
Judson A. Lehman - Scottsdale AZ
Assignee:

VLSI Technology, Inc. - San Jose CA
International Classification:

G06F 1500
US Classification:

395162
Abstract:

A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.