Julia E Brown

US Patent:

6504235, Jan 7, 2003

Filed:

Jun 6, 2001

Appl. No.:

09/876538

Inventors:

Adele E. Schmitz - Newbury Park CA
Julia J. Brown - Santa Monica CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01L 2358

US Classification:

257649, 257615

Abstract:

A semiconductor passivation technique uses a plasma enhanced chemical vapor deposition (PECVD) process to produce a silicon-rich nitride film as a passivation layer on a Group III-V semiconductor device. The silicon-rich film has a nitrogen to silicon ratio of about 0. 7, has a relatively high index of refraction of, for example, approximately 2. 4, is compressively stressed, and is very low in hydrogen and oxygen content.

US Patent:

63312573, Dec 18, 2001

Filed:

Nov 30, 1999

Appl. No.:

9/452052

Inventors:

Robert Y. Loo - Agoura Hills CA
Adele Schmitz - Newbury Park CA
Julia Brown - Santa Monica CA
James Foschaar - Thousand Oaks CA
Daniel J. Hyman - Cleveland Hts. OH
Tsung-Yuan Hsu - Westlake Village CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01B 1300
H01P 110
B44C 122

US Classification:

216 13

Abstract:

Methods for the design and fabrication of micro-electro-mechanical switches are disclosed. Two different switch designs with three different switch fabrication techniques are presented for a total of six switch structures. Each switch has a multiple-layer armature with a suspended biasing electrode and a conducting transmission line affixed to the structural layer of the armature. A conducting dimple is connected to the conducting line to provide a reliable region of contact for the switch. The switch is fabricated using silicon nitride as the armature structural layer and silicon dioxide as the sacrificial layer supporting the armature during fabrication. Hydrofluoric acid is used to remove the silicon dioxide layer with post-processing in a critical point dryer to increase yield.

US Patent:

59207736, Jul 6, 1999

Filed:

Jun 16, 1997

Appl. No.:

8/876277

Inventors:

Madjid Hafizi - Santa Monica CA
Julia J. Brown - Santa Monica CA
William E. Stanchina - Thousand Oaks CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01L 21338

US Classification:

438170

Abstract:

An integrated circuit technology combines heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs) and other components along with interconnect metallization on a single substrate. In a preferred embodiment a flat substrate is patterned, using dry etching, to provide one or more mesas in locations which will eventually support HEMTs. A device stack including HEMT and HBT layers is built up over the substrate by molecular beam epitaxy, with the active HEMT devices located on the mesas within openings in the HBT layer. In this way the active HEMT is aligned with the HBT layer to planarize the finished integrated circuit.

US Patent:

62286730, May 8, 2001

Filed:

May 13, 1999

Appl. No.:

9/311673

Inventors:

Robert Y. Loo - Agoura Hills CA
Adele E. Schmitz - Newbury Park CA
Julia J. Brown - Santa Monica CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01L 21302

US Classification:

438 57

Abstract:

A photodetector is fabricated in a multilayer structure having a semi-insulating InP substrate, an n+ InP contact layer overlying the InP substrate, an undoped InGaAs absorbing layer overlying the n+ InP contact layer, and a p+ doped InGaAs layer overlying the undoped InGaAs absorbing layer. A gold-beryllium p-contact dot is deposited onto the p+ doped InGaAs layer of the multilayer structure. A mesa structure is etched with a citric acid-based etchant into the multilayer structure. The mesa structure includes the metal p-contact dot, the p+ doped InGaAs layer, and the undoped InGaAs absorbing layer. The n+ InP contact layer is patterned, and a passive metallic n-contact layer is deposited onto the patterned n+ InP contact layer. A polyimide insulator layer overlying a portion of the structure is deposited and patterned, so that the polyimide insulator layer does not cover the passive metal p-contact dot and the metallic n-contact layer. The patterned organic polymer insulator layer is cured and the device is passivated by heating it in a nitrogen atmosphere.

US Patent:

63168200, Nov 13, 2001

Filed:

Aug 28, 1998

Appl. No.:

9/143680

Inventors:

Adele E. Schmitz - Newbury Park CA
Julia J. Brown - Santa Monica CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01L 2358

US Classification:

257649

Abstract:

A semiconductor passivation technique uses a plasma enhanced chemical vapor deposition (PECVD) process to produce a silicon-rich nitride film as a passivation layer on a Group III-V semiconductor device. The silicon-rich film has a nitrogen to silicon ratio of about 0. 7, has a relatively high index of refraction of, for example, approximately 2. 4, is compressively stressed, and is very low in hydrogen and oxygen content.

US Patent:

53592204, Oct 25, 1994

Filed:

Dec 22, 1992

Appl. No.:

7/994734

Inventors:

Lawrence E. Larson - Santa Monica CA
Peter Asbeck - San Diego CA
Julia J. Brown - Santa Monica CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H01L 2707
H01L 29205

US Classification:

257378

Abstract:

A hybrid power transistor (40) includes a vertical PNP bipolar transistor (42) having a floating base (46). A junction-gate type field-effect transistor (FET) (62) has a lateral N-type channel (64,66) and a vertical electron injection path (54) from the channel (64,66) into the base (46) of the bipolar transistor (42). The FET channel current and thereby the electron injection current are controlled by the FET gate voltage. The injection current conductivity modulates the base (46) and thereby controls the collector current of the bipolar transistor (42). The FET (62) may have a high electron mobility transistor (HEMT), junction-gate field-effect transistor (JFET) or metal-semiconductor field-effect transistor (MESFET) structure. The FET (62) does not require a gate insulating layer, enabling fabrication of the hybrid transistor (40) in the group III-V material system.

US Patent:

60466596, Apr 4, 2000

Filed:

May 15, 1998

Appl. No.:

9/080326

Inventors:

Robert Y. Loo - Agoura Hills CA
Adele Schmitz - Newbury CA
Julia Brown - Santa Monica CA
Jonathan Lynch - Oxnard CA
Debabani Choudhury - Woodland Hills CA
James Foschaar - Thousand Oaks CA
Daniel J. Hyman - Cleveland Hts. OH
Brett Warneke - Berkeley CA
Juan Lam - Agoura Hills CA
Tsung-Yuan Hsu - Westlake Village CA
Jae Lee - University Heights OH
Mehran Mehregany - Pepper Pike OH

Assignee:

Hughes Electronics Corporation - El Segundo CA
Rosemont Aerospace, Inc. - Burnsville MN

International Classification:

H01P 110
H01H 5700

US Classification:

333262

Abstract:

Methods for the design and fabrication of micro-electro-mechanical switches are disclosed. Two different switch designs with three different switch fabrication techniques are presented for a total of six switch structures. Each switch has a multiple-layer armature with a suspended biasing electrode and a conducting transmission line affixed to the structural layer of the armature. A conducting dimple is connected to the conducting line to provide a reliable region of contact for the switch. The switch is fabricated using silicon nitride as the armature structural layer and silicon dioxide as the sacrificial layer supporting the armature during fabrication. Hydrofluoric acid is used to remove the silicon dioxide layer with post-processing in a critical point dryer to increase yield.