Julie C Brewer

US Patent:

8031509, Oct 4, 2011

Filed:

Dec 18, 2009

Appl. No.:

12/653836

Inventors:

Lawrence Schloss - Palo Alto CA, US
Julie Casperson Brewer - Santa Clara CA, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Mountain View CA, US

International Classification:

G11C 11/00

US Classification:

365148, 365163

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

8031510, Oct 4, 2011

Filed:

Jul 6, 2010

Appl. No.:

12/803810

Inventors:

Lawrence Schloss - Palo Alto CA, US
Rene Meyer - Mountain View CA, US
Wayne Kinney - Emmett ID, US
Roy Lambertson - Los Altos CA, US
Julie Casperson Brewer - Santa Clara CA, US

International Classification:

G11C 11/00

US Classification:

365148

Abstract:

An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

US Patent:

8274817, Sep 25, 2012

Filed:

Oct 25, 2011

Appl. No.:

13/281335

Inventors:

Lawrence Schloss - Palo Alto CA, US
Julie Casperson Brewer - New York NY, US
Wayne Kinney - Emmett CA, US
Roy Lambertson - Los Altos CA, US
Rene Meyer - Atherton CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

G11C 11/00

US Classification:

365148, 365171

Abstract:

An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

US Patent:

8320161, Nov 27, 2012

Filed:

Oct 4, 2011

Appl. No.:

13/252932

Inventors:

Lawrence Schloss - Palo Alto CA, US
Julie Casperson Brewer - New York NY, US
Wayne Kinney - Emmett CA, US
Rene Meyer - Atherton CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

G11C 11/21

US Classification:

365148, 365163

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

8358529, Jan 22, 2013

Filed:

Nov 3, 2011

Appl. No.:

13/288433

Inventors:

Lawrence Schloss - Palo Alto CA, US
Julie Casperson Brewer - Santa Clara CA, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Atherton CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

G11C 11/00

US Classification:

365148, 257 4

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

US Patent:

8395928, Mar 12, 2013

Filed:

Aug 9, 2011

Appl. No.:

13/206460

Inventors:

Julie Casperson Brewer - Santa Clara CA, US
Christophe Chevallier - Palo Alto CA, US
Wayne Kinney - Emmett CA, US
Roy Lambertson - Los Altos CA, US
Darrell Rinerson - Cupertino CA, US
Lawrence Schloss - Palo Alto CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

G11C 11/36

US Classification:

365148, 257 4, 257E45003

Abstract:

A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

US Patent:

8493771, Jul 23, 2013

Filed:

Aug 9, 2012

Appl. No.:

13/570871

Inventors:

Lawrence Schloss - Palo Alto CA, US
Julie Casperson Brewer - New York NY, US
Wayne Kinney - Emmett ID, US
Roy Lambertson - Los Altos CA, US
Rene Meyer - Atherton CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

G11C 11/21

US Classification:

365148, 365163

Abstract:

An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

US Patent:

8565006, Oct 22, 2013

Filed:

Dec 18, 2012

Appl. No.:

13/719106

Inventors:

Lawrence Schloss - Palo Alto CA, US
Julie Casperson Brewer - New York NY, US
Wayne Kinney - Emmett ID, US
Rene Meyer - Atherton CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

G11C 13/00

US Classification:

365148, 365163

Abstract:

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).