Bass, Berry & Sims, PLC 150 Third Avenue South Suite 2800, Nashville, TN 37201 (615)7427722 (Office), (615)7422865 (Fax)
Licenses:
Tennessee - Active 1999
Education:
Vanderbilt University Law School Degree - JD - Juris Doctor - Law Graduated - 1999 Eckerd College Degree - BA - Bachelor of Arts - Business Management Graduated - 1996
Julie M. Walker - El Dorado Hills CA, US Doyle Rivers - El Dorado Hills CA, US
International Classification:
G11C 7/00 G11C 7/10 G11C 17/00
US Classification:
365 94, 365189011, 36518902
Abstract:
An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.
Managing Threshold Voltage Shift In Nonvolatile Memory
- Santa Clara CA, US Rajesh Sundaram - Folsom CA, US Prashant S. Damle - Santa Clara CA, US Doyle Rivers - El Dorado Hills CA, US Julie M. Walker - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 13/00
Abstract:
Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
Julie M. Walker - El Dorado Hills CA, US Doyle Rivers - El Dorado Hills CA, US
International Classification:
G11C 8/04
US Classification:
365239
Abstract:
A shared-signaling multi-device memory system is capable of changing between addressing modes without the multi-device memory being required to undergo a power cycle. First and second registers of a memory device are set to both contain first address-identification information in response a first address-assignment command that is received a power cycle. The first register is set to contain second address-identification information in response a second address-assignment command that is received subsequently to the first address assignment command. Depending on the value of the second address-identification information, the memory device is configured in an individual-device-addressing mode or a parallel addressing mode without a power cycle. The first register can be reset to the first address-identification information contained in the second register in response to an address-restore command without a power cycle. A corresponding method is also disclosed.
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Julie W Walker Amusement/Recreation Services · Business Services at Non-Commercial Site