Julie A Walker from Derby, KS, age 68

Vector Haptic Feedback By Perceptual Combination Of Cues From Mechanically Isolated Actuators
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US Patent:

20190334426, Oct 31, 2019
Filed:

Nov 29, 2017
Appl. No.:

16/462224
Inventors:

- Stanford CA, US
Allison M. Okamura - Mountain View CA, US
Julie Walker - Stanford CA, US
International Classification:

H02K 33/18
G08B 6/00
A63F 13/285
Abstract:

Vector haptic feedback cues are provided by combining force cues from two or more 1-D actuators driven with asymmetric vibrations. In order for this combination to work properly, it is important for the actuators being combined to be mechanically isolated from each other. This combination can be a perceptual combination of force cues provided to different locations on the same body part of a user.

Reduced Uncorrectable Memory Errors
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US Patent:

20160188409, Jun 30, 2016
Filed:

Sep 3, 2015
Appl. No.:

14/844843
Inventors:

- Santa Clara CA, US
Prashant S. Damle - Santa Clara CA, US
Rajesh Sundaram - Folsom CA, US
Shekoufeh Qawami - El Dorado Hills CA, US
Julie M. Walker - El Dorado Hills CA, US
Doyle Rivers - El Dorado Hills CA, US
Assignee:

INTEL CORPORATION - Santa Clara CA
International Classification:

G06F 11/10
G06F 3/06
Abstract:

Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Reduced Uncorrectable Memory Errors
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US Patent:

20140258804, Sep 11, 2014
Filed:

Mar 11, 2013
Appl. No.:

13/792597
Inventors:

Kiran Pangal - Fremont CA, US
Prashant S. Damle - Santa Clara CA, US
Rajesh Sundaram - Folsom CA, US
Shekoufeh Qawami - El Dorado Hills CA, US
Julie M. Walker - El Dorado Hills CA, US
Doyle Rivers - El Dorado Hills CA, US
International Classification:

H03M 13/05
US Classification:

714752
Abstract:

Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.