Jun D Chen

US Patent:

6541946, Apr 1, 2003

Filed:

Mar 19, 2002

Appl. No.:

10/102501

Inventors:

Jun Chen - Allen TX
Xiaoyu Xi - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 140

US Classification:

323280, 323281, 323274

Abstract:

The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier having a first input coupled to a reference voltage node V ; a second amplifier having an input coupled to an output of the first amplifier ; a pass transistor having a control node coupled to an output of the second amplifier ; a feedback circuit and having an input coupled to the pass transistor and an output coupled to a second input of the first amplifier ; an inverting gain stage coupled to the input of the second amplifier ; and a high pass filter , and coupled between a power supply node and a control node of the inverting gain stage. The circuit uses the high pass filter , and and inverting gain stage to feedforward the power supply ripple into the LDOs control loop which counter-acts the impact of the supply ripple on the output node V.

US Patent:

6690228, Feb 10, 2004

Filed:

Dec 11, 2002

Appl. No.:

10/316340

Inventors:

Jun Chen - Allen TX
Siew Kuok Hoon - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 302

US Classification:

327538, 327541, 327542, 323313

Abstract:

A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A first bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a predetermined size, is arranged to conduct a collector current from the first mirror transistor. A second bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a size that is proportional to the size of the emitter area of the first bipolar transistor, is arranged to conduct a collector current from the second mirror transistor, the base thereof being connected to the collector thereof. A first resistor is provided, in series with the collector of the second bipolar transistor and the second mirror transistor. The base of the first bipolar transistor is coupled to a common connection node of the first resistor and the second mirror transistor to substantially reduce the effects of offset error in the holding circuit.

US Patent:

6844772, Jan 18, 2005

Filed:

Dec 11, 2002

Appl. No.:

10/316495

Inventors:

Siew Kuok Hoon - Dallas TX, US
Jun Chen - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 110

US Classification:

327541, 327539, 327543, 323315, 323316

Abstract:

A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A third, MOS transistor having a source and a gate, and a resistor circuit, together adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, are coupled to the second transistor and to the first input of the holding circuit. A fourth, MOS transistor coupled to the first transistor and to the second input of the subtracting circuit through a second resistor circuit is adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit. A second current mirror coupled to the first current mirror is adapted to cause a current to flow through a third resistor circuit that corresponds to the current through the first current mirror to thereby provide an output voltage corresponding to the threshold voltage.

US Patent:

6897637, May 24, 2005

Filed:

Dec 9, 2002

Appl. No.:

10/314931

Inventors:

Jun Chen - Allen TX, US
Siew K. Hoon - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F001/618

US Classification:

323274, 323303

Abstract:

A low drop-out voltage regulator uses a voltage subtractor circuit to form a power supply rejection boost circuit. The voltage subtractor is inserted between the pass element and the amplifier of the low drop-out regulator. The voltage regulator circuit includes a pass element coupled between an input node and an output node; a voltage feedback circuit and coupled to the output node Vo; an amplifier having an input coupled to the voltage feedback circuit; and a voltage subtractor having a control node coupled to an output of the amplifier , an output coupled to a control node of the pass element , and an input coupled to the input node. The boost circuit improves supply noise rejection performance significantly without adding much complexity to the regulator system. The boost circuit is simple and consumes negligible silicon area and power.

US Patent:

6903539, Jun 7, 2005

Filed:

Nov 19, 2003

Appl. No.:

10/716958

Inventors:

Jun Chen - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F003/16

US Classification:

323315, 327530, 327362

Abstract:

System for a current source with enhanced output impedance. A preferred embodiment comprises a cascode current source arranged in a current mirror configuration (such as current source ) with a pair of level shifters arranged in a source-follower configuration (such as level shifters and ). The level shifters reduce the compliance voltage of the current source, permitting use in low voltage applications.

US Patent:

6967508, Nov 22, 2005

Filed:

Mar 4, 2004

Appl. No.:

10/794833

Inventors:

Jian Zhou - Plano TX, US
Jun Chen - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K023/54

US Classification:

327122, 327116

Abstract:

The frequency doubling circuit and method provides an output signal with stable frequency and a 50% duty cycle. The frequency of the output signal is two times a frequency of the input signal. The circuit only requires four comparators, eight small capacitors, and some switches and transistors for frequency doubling applications. With the help of feedforward structure, the circuit has an almost-instantaneous response. The performance of the provided frequency doubling circuit and method is independent of the frequency and duty cycle of input signal, power supply voltage, temperature, and process variations.

US Patent:

7042200, May 9, 2006

Filed:

Apr 7, 2003

Appl. No.:

10/408530

Inventors:

Jun Chen - Allen TX, US
Keith Kunz - Bryan TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 1/40

US Classification:

323283

Abstract:

The present invention provides improved line and load regulation of a switching-mode power converter () without requiring additional capacitors (), either internally or externally, to stabilize the control loop. The present invention can provide this by integrating a digital compensator () with the pulse-width modulator (“PWM”) of the switching-mode power converter. Such a compensator () can include comparators ( and ), digital circuits (), and resistors (, and ).

US Patent:

7061214, Jun 13, 2006

Filed:

Nov 25, 2003

Appl. No.:

10/722270

Inventors:

Valerian Mayega - Dallas TX, US
Jun Chen - Allen TX, US
James L. Krug - Carrollton TX, US
David W. Evans - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 1/577

US Classification:

323267

Abstract:

A single-inductor dual-output buck converter and control method that facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of which can be configured to provide a selected/desired voltage by selection of respective duty cycles. The topology of the inverter includes a pair of diodes or switches that can selectively re-circulate inductor current. The converter is generally operated at a fixed frequency with four stages of operation. A first and third stage of operation provide power to a first and second output, respectively. A second and fourth stage of operation re-circulate inductor current and can partially recharge a battery type power source. The power output for each stage (voltage and current) can be selectively obtained by computing and employing appropriate time periods for the stages of operation that correspond to appropriate duty cycles.