Jung Y Ahn from Austin, TX, age 35

Us Patents

Synchronous Optical Bus Providing Communication Between Computer System Components
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US Patent:

8032033, Oct 4, 2011
Filed:

Oct 23, 2007
Appl. No.:

11/977369
Inventors:

Nathan Binkert - Redwood City CA, US
Norm Jouppi - Palo Alto CA, US
Robert Schreiber - Palo Alto CA, US
Jung Ho Ahn - Palo Alto CA, US
Moray McLaren - Bristol, GB
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

H04B 10/20
US Classification:

398155, 398164, 398168
Abstract:

A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.

Three-Dimensional Memory Module Architectures
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US Patent:

8059443, Nov 15, 2011
Filed:

Oct 23, 2007
Appl. No.:

11/975963
Inventors:

Moray McLaren - Bristol, GB
Jung Ho Ahn - Palo Alto CA, US
Alan Lynn Davis - Coalville CA, US
Nathan Lorenzo Binkert - Redwood CA, US
Norman Paul Jouppi - Palo Alto CA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G11C 13/04
US Classification:

365 64, 36523003, 365 51
Abstract:

Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e. g. , through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.

Two-Phase Optical Communication Methods And Optical Bus Systems For Implementing The Same
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US Patent:

8472802, Jun 25, 2013
Filed:

Mar 10, 2008
Appl. No.:

12/921763
Inventors:

Jung Ho Ahn - Palo Alto CA, US
Moray McLaren - Bristol, GB
Alan L. Davis - Coalville CA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

H04J 14/02
US Classification:

398 69, 398213
Abstract:

Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted () from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.

Intentionally Skewed Optical Clock Signal Distribution
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US Patent:

8543005, Sep 24, 2013
Filed:

Apr 30, 2008
Appl. No.:

12/990494
Inventors:

Nathan L. Binkert - Redwood City CA, US
Norman P. Jouppi - Palo Alto CA, US
Robert S. Schreiber - Palo Alto CA, US
Jung Ho Ahn - Palo Alto CA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

H04B 10/00
US Classification:

398155, 398154, 398158, 398159, 398 66, 398 33, 398177, 398 34, 385 24, 385 14, 385 31, 385129, 370503, 370400, 370535, 375354, 375356, 375260
Abstract:

Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node.

Optoelectronic Switches Using On-Chip Optical Waveguides
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US Patent:

20110069963, Mar 24, 2011
Filed:

Mar 11, 2008
Appl. No.:

12/921768
Inventors:

Moray McLaren - Bristol, GB
Jung Ho Ahn - Palo Alto CA, US
Nathan L. Binkert - Palo Alto CA, US
Alan L. Davis - Palo Alto CA, US
Norman P. Jouppi - Palo Alto CA, US
International Classification:

H04B 10/00
G02B 6/35
US Classification:

398115, 385 16
Abstract:

Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

Dynamic Utilization Of Power-Down Modes In Multi-Core Memory Modules
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US Patent:

20110138387, Jun 9, 2011
Filed:

Aug 13, 2008
Appl. No.:

13/058067
Inventors:

Jung Ho Ahn - Menlo Park CA, US
Norman P. Jouppi - San Mateo CA, US
Jacob B. Leverich - San Mateo CA, US
Robert S. Schreiber - Palo Alto CA, US
Assignee:

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. - Houston TX
International Classification:

G06F 9/00
G06F 9/455
US Classification:

718 1, 713100
Abstract:

Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric () that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (), the method also includes collecting usage information () associated with the virtual memory device over a period of time, determining an operation mode () for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode ().

Independently Controlled Virtual Memory Devices In Memory Modules
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US Patent:

20110145493, Jun 16, 2011
Filed:

Aug 8, 2008
Appl. No.:

13/058188
Inventors:

Jung Ho Ahn - Palo Alto CA, US
Norman P. Jouppi - Palo Alto CA, US
Jacob B. Erich - San Mateo CA, US
International Classification:

G06F 12/00
G06F 12/08
US Classification:

711105, 711154, 711129, 711E12023, 711E12001
Abstract:

Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module () includes at least one virtual memory device and a demultiplexer register () disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.