Jung Sok Cho

US Patent:

7274690, Sep 25, 2007

Filed:

Nov 22, 2002

Appl. No.:

10/302436

Inventors:

Sung Soo Park - Cupertino CA, US
Sung Man Park - Cupertino CA, US
Jung Wook Cho - Sunnyvale CA, US
Edward Pak - Saratoga CA, US

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

H04L 12/50
H04L 12/56
H04Q 11/00
G06F 13/00

US Classification:

370388, 3703954, 370408, 370412, 370429, 710317

Abstract:

A content addressable merged queue (camQ) architecture for high-speed switch fabrics reduces the memory requirement for crossbar switch input and output queues using memory cells and age tag comparators. CamQ emulates VOQ FIFO for each supporting priority, eliminating HOL blocking. Multiple QoS levels are supported cost effectively at higher traffic bandwidth limits. Content addressable memory (CAM) cells store payload destinations, which can be addressed by cell priorities. Once a priority for QoS is decided, all the cells with the selected priority in the payload can make connection requests to destination ports directly through the CAM structure. An age tag is assigned to incoming cells and fast age tag comparators provide FCFS features by selecting the oldest cell. Small memory sizes prevent the bottlenecking in ingress and egress queues. A CIOQ crossbar has a fast switching speed, emulating a FIFO output queue switch.

US Patent:

7352764, Apr 1, 2008

Filed:

Jan 21, 2004

Appl. No.:

10/762950

Inventors:

Sung Soo Park - Cupertino CA, US
Sung Man Park - Kyungkido, KR
Jung Wook Cho - Sunnyvale CA, US

Assignee:

Silicon Image, Inc. - Sunnyvale CA

International Classification:

H04L 12/28

US Classification:

370412, 370389, 711108, 365 49

Abstract:

A content addressable merged queue (camQ) architecture for switching data. The camQ architecture comprises a first array of priority cells for indicating a priority of a plurality of cells and a second array of destination cells for indicating a destination of the plurality of cells. A priority selector is operable to select a portion of said plurality of cells according to a priority selection. A grant generator is operable to grant at least one connection request associated with cells of the portion.

US Patent:

8271812, Sep 18, 2012

Filed:

Apr 7, 2010

Appl. No.:

12/756006

Inventors:

Josh P. de Cesare - Campbell CA, US
Jung Wook Cho - Cupertino CA, US
Toshi Takayanagi - San Jose CA, US
Timothy J. Millet - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 1/00
G06F 1/26
G06F 3/038
G06F 3/00
G09G 3/18
G11C 5/14
H04M 1/00

US Classification:

713300, 713320, 713323, 713324, 345 52, 345211, 365227, 455574, 719321

Abstract:

In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

US Patent:

8443216, May 14, 2013

Filed:

Aug 21, 2012

Appl. No.:

13/590217

Inventors:

Josh P. de Cesare - Campbell CA, US
Jung Wook Cho - Cupertino CA, US
Toshi Takayanagi - San Jose CA, US
Timothy J. Millet - Moutain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 1/00
G06F 1/26
G06F 3/038
G06F 3/00
G09G 3/18
G11C 5/14
H04M 1/00

US Classification:

713300, 713320, 713323, 713324, 345 52, 345211, 365227, 455574, 719321

Abstract:

In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

US Patent:

8508621, Aug 13, 2013

Filed:

Sep 30, 2010

Appl. No.:

12/895346

Inventors:

Guy Côté - San Jose CA, US
Jeffrey E. Frederiksen - Sunnyvale CA, US
Joseph P. Bratt - San Jose CA, US
Jung Wook Cho - Cupertino CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H04N 5/76

US Classification:

34823199, 3482221

Abstract:

Certain embodiments of the present disclosure provide a flexible memory input/output controller that is configured to the storing and reading of multiple types of pixels and pixel memory formats. For instance, the memory I/O controller may support the storing and reading of raw image pixels at various bits of precision, such as 8-bit, 10-bit, 12-bit, 14-bit, and 16-bit. Pixel formats that are unaligned with memory bytes (e. g. , not being a multiple of 8-bits) may be stored in a packed manner. The memory I/O controller may also support various formats of RGB pixel sets and YCC pixel sets.

US Patent:

20130042135, Feb 14, 2013

Filed:

Aug 12, 2011

Appl. No.:

13/208669

Inventors:

Herbert Lopez-Aguado - Sunnyvale CA, US
Jung Wook Cho - Cupertino CA, US
Conrad H. Ziesler - Seattle WA, US

International Classification:

G06F 1/12

US Classification:

713400

Abstract:

A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.

US Patent:

20130043917, Feb 21, 2013

Filed:

Aug 16, 2011

Appl. No.:

13/211004

Inventors:

Josh P. de Cesare - Campbell CA, US
Jung Wook Cho - Cupertino CA, US
Toshinari Takayanagi - San Jose CA, US

International Classification:

H03L 7/07

US Classification:

327150

Abstract:

A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL.

US Patent:

20130076381, Mar 28, 2013

Filed:

Sep 26, 2011

Appl. No.:

13/245229

Inventors:

Toshinari Takayanagi - San Jose CA, US
Jung Wook Cho - Cupertino CA, US

International Classification:

G01R 31/00
G01K 15/00

US Classification:

32475003, 374 1, 374E15001

Abstract:

A method and apparatus for temperature sensor calibration is disclosed. In one embodiment, an integrated circuit (IC) is tested at a first known temperature corresponding to a first temperature threshold. During the test, a first temperature reading is obtained from a temperature sensor. A first offset is calculated by determining the difference between the first known temperature and the first temperature reading. The first offset is recorded in a storage unit for later use during operation of the IC. During operation, the first offset may be added to temperature readings obtained from a temperature sensing unit to produce an adjusted temperature value. The adjusted temperature value may be compared to one or more temperature thresholds. Based on the comparisons, a power management unit may perform power control actions.