Jung Hwa Son

US Patent:

20120201085, Aug 9, 2012

Filed:

Apr 19, 2011

Appl. No.:

13/089486

Inventors:

Myung Chan Choi - San Jose CA, US
Young Tae Kim - San Jose CA, US
Jung Ju Son - Santa Clara CA, US
Sang-Kyun Han - Sunnyvale CA, US
Sun Hyoung Lee - Seoul, KR

Assignee:

ZMOS TECHNOLOGY, INC. - Sunnyvale CA

International Classification:

G11C 7/10
G11C 7/00

US Classification:

36518905, 365222, 365203

Abstract:

Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.