Junichi Shiozawa

US Patent:

56708050, Sep 23, 1997

Filed:

May 7, 1996

Appl. No.:

8/643983

Inventors:

Erwin Hammerl - Stormville NY
Jack A. Mandelman - Stormville NY
Herbert L. Ho - Washingtonville NY
Junichi Shiozawa - Wappingers Falls NY
Reinhard Johannes Stengl - Wappingers Falls NY

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki
International Business Machines Corporation - Armonk NY
Siemens, Aktiengesellschaft - Munich

International Classification:

H01L 27108
H01L 2976
H01L 2994

US Classification:

257301

Abstract:

A semiconductor memory device includes a trench formed in a semiconductor substrate. Conductive material is formed in the trench and is insulatively spaced from the semiconductor substrate to form a capacitor. A transfer gate transistor includes source/drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions. A buried strap electrically connects the capacitor to one of the source/drain regions of the transfer gate transistor. A portion of the buried strap includes recrystallized silicon.

US Patent:

55433480, Aug 6, 1996

Filed:

Mar 29, 1995

Appl. No.:

8/412442

Inventors:

Erwin Hammerl - Stormville NY
Jack A. Mandelman - Stormville NY
Herbert L. Ho - Washingtonville NY
Junichi Shiozawa - Wappingers Falls NY
Reinhard J. Stengl - Wappingers Falls NY

Assignee:

Kabushiki Kaisha Toshiba - Kawasaki
Siemens Aktiengesellschaft - Munich
International Business Machines Corp. - Armonk NY

International Classification:

H01L 218242

US Classification:

437 60

Abstract:

A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized.