Juraj Obert

US Patent:

20130328895, Dec 12, 2013

Filed:

Jun 7, 2013

Appl. No.:

13/912946

Inventors:

Eric Zolnowski - Deltona FL, US
Pierre Boudier - Foix, FR
Juraj Obert - Oviedo FL, US

International Classification:

G06T 1/00

US Classification:

345522

Abstract:

Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.

US Patent:

20200327715, Oct 15, 2020

Filed:

Jun 29, 2020

Appl. No.:

16/915340

Inventors:

- Santa Clara CA, US
Eric Zolnowski - Orlando FL, US
Pierre Boudier - Los Gatos CA, US
Juraj Obert - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G06T 15/00
G06T 1/00
G06T 1/20
G06T 1/60
G06T 11/40
G06T 15/80
G06T 17/20
G06T 19/20

Abstract:

A method and system for performing graphics processing is provided. The method and system includes storing stencil buffer values in a stencil buffer; generating either or both of a reference value and a source value in a fragment shader; comparing the stencil buffer values against the reference value; and processing a fragment based on the comparing the stencil buffer values against the reference value.

US Patent:

20180293761, Oct 11, 2018

Filed:

Jun 12, 2018

Appl. No.:

16/006502

Inventors:

- San Diego CA, US
Vineet Goel - San Diego CA, US
Juraj Obert - Orlando FL, US
Liang Li - San Diego CA, US

International Classification:

G06T 11/00
G06T 15/00

Abstract:

Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.

US Patent:

20170249779, Aug 31, 2017

Filed:

Feb 25, 2016

Appl. No.:

15/053930

Inventors:

- San Diego CA, US
Juraj Obert - Orlando FL, US

International Classification:

G06T 15/80
G06T 15/06

Abstract:

At least one processor may organize a plurality of primitives of a scene in a hierarchical data structure, wherein a plurality of bounding volumes are associated with a plurality of nodes of the hierarchical data structure. The at least one processor may rasterize a representation of each of the plurality of bounding volumes to an off-screen render target in the memory. The at least one processor may determine, based at least in part on a pixel in the off-screen render target that maps to a ray in the scene, a non-root node of the hierarchical data structure associated with the pixel as a start node to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine whether the ray in the scene intersects one of the plurality of primitives.

US Patent:

20170243375, Aug 24, 2017

Filed:

Feb 18, 2016

Appl. No.:

15/047472

Inventors:

- San Diego CA, US
Vineet Goel - La Jolla CA, US
Juraj Obert - Orlando FL, US
Liang Li - San Diego CA, US

International Classification:

G06T 11/00

Abstract:

Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.

US Patent:

20170061670, Mar 2, 2017

Filed:

Oct 31, 2016

Appl. No.:

15/339860

Inventors:

- Sunnyvale CA, US
Eric Zolnowski - Orlando FL, US
Pierre Boudier - Los Gatos CA, US
Juraj Obert - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 15/00
G06T 17/20
G06T 15/80
G06T 1/20
G06T 19/20
G06T 11/40
G06T 1/60

Abstract:

Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.

US Patent:

20160364901, Dec 15, 2016

Filed:

Jun 12, 2015

Appl. No.:

14/738535

Inventors:

- San Diego CA, US
Christopher Paul Frascati - Oviedo FL, US
Juraj Obert - Orlando FL, US
Hitendra Mohan Gangani - Orlando FL, US
Avinash Seetharamaiah - San Diego CA, US

International Classification:

G06T 15/06
G06T 1/20
G06T 1/60
G06T 15/40

Abstract:

A method and apparatus for ray tracing may include a method, manufacture and apparatus for ray tracing that may include dividing a render target into a plurality of bins. Next, a visibility pass is performed using ray tracing to generate a visibility stream such that the visibility stream indicates, for each bin of the plurality of bins, which primitives are visible in the bin. Then, for at least one bin of the plurality of bins, each primitive in the bin that is indicated in the visibility stream as being visible in the bin is rendered.

US Patent:

20160350892, Dec 1, 2016

Filed:

Sep 16, 2015

Appl. No.:

14/855962

Inventors:

- San Diego CA, US
Vineet Goel - La Jolla CA, US
Young In Yeo - Orlando FL, US
Juraj Obert - Orlando FL, US

International Classification:

G06T 1/20
G06T 15/80
H04N 13/04
G06T 15/00
H04N 13/02
H04N 13/00

Abstract:

Techniques are described for stereoscopic view generation. A graphics processing unit (GPU) may combine attribute information for two or more corresponding vertices of corresponding primitives in different views. The GPU may process the combined attributed information to generate graphics data for the stereoscopic view.

Address:

1433 Pon Pon Ct, Orlando, FL 32825

VIN:

WBAWB73517PV82550

Make:

BMW

Model:

3 SERIES

Year:

2007