Justin Chenghung Chen

US Patent:

7792113, Sep 7, 2010

Filed:

Oct 21, 2002

Appl. No.:

10/274608

Inventors:

Venkateshwar R. Pullela - San Jose CA, US
Justin Q. Chen - Palo Alto CA, US
Robert C. Benea - Santa Clara CA, US
Maurizio Portolani - Milpitas CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370392

Abstract:

A method of operating a network is disclosed. The method includes identifying a packet as being subject to a policy and forwarding said packet based on said policy, if said packet is subject to said policy.

US Patent:

7830898, Nov 9, 2010

Filed:

Mar 7, 2008

Appl. No.:

12/044311

Inventors:

Justin Qizhong Chen - Palo Alto CA, US
Ambarish Chintamani Kenghe - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/56
G06F 15/16

US Classification:

370401, 709232, 726 13, 726 26

Abstract:

A method for inspecting packets is disclosed. The method includes processing a packet by determining if the packet is an inter-layer binding protocol packet and inspecting the packet, if the packet is an inter-layer binding protocol packet. The inter-layer binding protocol packet indicating a binding between a first network layer address and a second network layer address.

US Patent:

20040022253, Feb 5, 2004

Filed:

Jul 31, 2002

Appl. No.:

10/210190

Inventors:

Justin Chen - Palo Alto CA, US
Ambarish Kenghe - San Jose CA, US

International Classification:

H04L012/28

US Classification:

370/395540

Abstract:

A method for inspecting packets is disclosed. The method includes processing a packet by determining if the packet is an inter-layer binding protocol packet and inspecting the packet, if the packet is an inter-layer binding protocol packet. The inter-layer binding protocol packet indicating a binding between a first network layer address and a second network layer address.

US Patent:

20210326505, Oct 21, 2021

Filed:

Apr 5, 2021

Appl. No.:

17/222132

Inventors:

- Santa Clara CA, US
Khurram Zafar - San Jose CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Rong Lv - Shanghai, CN
Justin Chen - Milpitas CA, US
Abhishek Vikram - Santa Clara CA, US
Yuan Xu - Sunnyvale CA, US
Ping Zhang - Saratoga CA, US

International Classification:

G06F 30/3323
G06N 5/04
G03F 7/20

Abstract:

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

US Patent:

20210018912, Jan 21, 2021

Filed:

Apr 10, 2019

Appl. No.:

16/461579

Inventors:

- SAN JOSE CA, US
Melonee Wise - San Jose CA, US
Nadir Muzaffar - San Jose CA, US
Jenna Guergah - San Jose CA, US
Russell Toris - San Jose CA, US
Michael Ferguson - Concord NH, US
Rodion W. Romantsov - San Jose CA, US
Michael Hwang - San Jose CA, US
Jiahao Feng - Castro Valley CA, US
Justin Chen - San Jose CA, US
Sarah Eliott - Mountain View CA, US
Derek King - San Jose CA, US
John W. Stewart - San Francisco CA, US

Assignee:

FETCH ROBOTICS, INC. - SAN JOSE CA

International Classification:

G05D 1/00
G05D 1/02
G06F 3/0482

Abstract:

A robot management system includes: a server; a plurality of robots operably connected to the server over a network, at least one robot including a sensor; and a graphic user interface (GUI) operably connected to the server, the GUI configured to display a map of a facility comprising the plurality of robots, the map configured to receive from a user the user's instructions to manage the robot.

US Patent:

20200097621, Mar 26, 2020

Filed:

Nov 26, 2019

Appl. No.:

16/696554

Inventors:

- Santa Clara CA, US
Khurram Zafar - San Jose CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Rong Lv - Shanghai, CN
Justin Chen - Milpitas CA, US
Abhishek Vikram - Santa Clara CA, US
Yuan Xu - Sunnyvale CA, US
Ping Zhang - Saratoga CA, US

International Classification:

G06F 17/50
G03F 7/20
G06N 5/04

Abstract:

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

US Patent:

20180300434, Oct 18, 2018

Filed:

Apr 3, 2018

Appl. No.:

15/944080

Inventors:

- Santa Clara CA, US
Khurram Zafar - San Jose CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Rong Lv - Shanghai, CN
Justin Chen - Milpitas CA, US
Abhishek Vikram - Santa Clara CA, US
Yuan Xu - Sunnyvale CA, US
Ping Zhang - Saratoga CA, US

International Classification:

G06F 17/50
G06N 99/00
G06N 5/04
G03F 7/20

Abstract:

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

US Patent:

20180033132, Feb 1, 2018

Filed:

Sep 20, 2017

Appl. No.:

15/709856

Inventors:

- San Clara CA, US
Chenmin Hu - Saratoga CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Chingyun Hsiang - Cupertino CA, US
Justin Chen - Milpitas CA, US
Raymond Xu - Sunnyvale CA, US
Abhishek Vikram - Santa Clara CA, US
Ping Zhang - Saratoga CA, US

International Classification:

G06T 7/00
G06K 9/46
G06K 9/52
G06K 9/62

Abstract:

Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.