Justin E Poarch

US Patent:

7339275, Mar 4, 2008

Filed:

Nov 22, 2004

Appl. No.:

10/995818

Inventors:

James Jen Ho Wang - Phoenix AZ, US
Justin E. Poarch - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48

US Classification:

257777, 257686, 257E25013, 438108, 438109

Abstract:

Multi-chip semiconductor device assemblies and methods for fabricating such assemblies are provided. An exemplary assembly comprises a first chip having a first surface and comprising a plurality of conductive pads disposed at the first surface and a plurality of circuits. Each of the pads is electrically coupled to one of the circuits. A second chip having a second surface is disposed adjacent to the first surface of the first chip. The second chip comprises a plurality of bonding members disposed at the second surface. Each of the bonding members is connected to a corresponding pad. The second chip is electrically coupled to at least one of the circuits via a corresponding pad and a corresponding bonding member. The second chip comprises a first and a second portion. The first portion overlies at least a portion of the first chip and the second portion extends beyond the first chip.

US Patent:

7868729, Jan 11, 2011

Filed:

Mar 3, 2009

Appl. No.:

12/397112

Inventors:

James Jen-Ho Wang - Phoenix AZ, US
Carl E. D'Acosta - Mesa AZ, US
Justin E. Poarch - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01F 5/00

US Classification:

336223, 336200, 336232, 296021

Abstract:

A stacked semiconductor device assembly () includes a device () having conductive traces () formed therein, and conductive interconnects () electrically connected to the conductive traces (). Another device () has conductive traces () formed therein and device pads () formed on an outer surface () of the device (). A method () entails attaching () a magnetic core () to an outer surface () of the device () and forming () the conductive interconnects () on the outer surface () using a stud bumping technique such that the interconnects () surround the magnetic core (). The conductive interconnects () are coupled () with the device pads () using thermocompression bonding to couple the device () with the device () to form a continuous device coil () wrapped around the magnetic core () from an alternating electrical connection of the traces (), the conductive interconnects (), and the traces ().

US Patent:

7892950, Feb 22, 2011

Filed:

Apr 29, 2009

Appl. No.:

12/432540

Inventors:

Alan J. Magnus - Gilbert AZ, US
Justin E. Poarch - Gilbert AZ, US
Jason R. Wright - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/46
H01L 21/78
H01L 21/301

US Classification:

438464, 257E21238, 438458, 438462, 438465

Abstract:

A method () for processing a panel () during semiconductor device () fabrication entails forming grooves () in a surface () of the panel () coincident with a dicing pattern () for the panel (). The grooves () extend partially through the panel () so that the panel () remains intact. The grooves () relieve stress in the panel () to reduce panel () warpage, thus enabling the panel () to be reliably held on a support structure () via vacuum when undergoing further processing, such as solder printing (). The method () further entails, dicing () through the panel () from the surface () in accordance with the dicing pattern () while the panel () is mounted on the support structure () to singularize the semiconductor devices ().

US Patent:

20050136558, Jun 23, 2005

Filed:

Dec 18, 2003

Appl. No.:

10/739605

Inventors:

James Wang - Phoenix AZ, US
Alan Magnus - Gilbert AZ, US
Justin Poarch - Gilbert AZ, US

International Classification:

H01L021/00
H01L023/48
H01L023/52
H01L029/40

US Classification:

438005000, 257734000

Abstract:

One embodiment relates to using a robust metal layer of a semiconductor device to form landing pads. In one embodiment, a sputterable, nonwettable refractory metal is used as a solder mask for the landing pads. A second device may then be coupled to the robust metal layer landing pads of the semiconductor device. In one embodiment, the landing pads are formed while the semiconductor device is in wafer form, and a second device is then coupled to the landing pads of each of the plurality of semiconductor devices within the wafer, such that each semiconductor device within the wafer is electrically coupled to a second device. In this manner, each semiconductor device within the wafer and its corresponding second device may be probed and tested as a system. After probing and testing, the wafer may be singulated into a plurality of individual device assemblies which may then be packaged.

US Patent:

20130207255, Aug 15, 2013

Filed:

Feb 15, 2012

Appl. No.:

13/397034

Inventors:

Alan J. Magnus - Gilbert AZ, US
Carl E.D. Acosta - Mesa AZ, US
Douglas G. Mitchell - Tempe AZ, US
Justin E. Poarch - Gilbert AZ, US

International Classification:

H01L 21/60
H01L 23/34
H01L 21/56

US Classification:

257712, 438122, 438119, 257E2308, 257E21502, 257E2151, 257E21514

Abstract:

A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive.

US Patent:

20140001616, Jan 2, 2014

Filed:

Jun 29, 2012

Appl. No.:

13/537392

Inventors:

Dwight L. DANIELS - Phoenix AZ, US
Stephen R. HOOPER - Mesa AZ, US
Alan J. MAGNUS - Gilbert AZ, US
Justin E. POARCH - Gilbert AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 23/495
H01L 21/60

US Classification:

257676, 438112, 257666, 257E21506, 257E23031

Abstract:

A structure and method to improve saw singulation quality and wettability of integrated circuit packages () assembled with lead frames () having half-etched recesses () in leads. A method of forming a semiconductor device package includes providing a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the strip.

US Patent:

20190206759, Jul 4, 2019

Filed:

Mar 7, 2019

Appl. No.:

16/295962

Inventors:

- Austin TX, US
Mahesh K. Shah - Scottsdale AZ, US
Lu Li - Gilbert AZ, US
David Abdo - Scdottsdale AZ, US
Geoffrey Tucker - Tempe AZ, US
Carl Emil D'Acosta - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
Justin Eugene Poarch - Gilbert AZ, US
Paul Hart - Phoenix AZ, US

International Classification:

H01L 23/367
H01L 21/48
H01L 23/13
H01L 23/528
H01L 23/00

Abstract:

Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.

US Patent:

20150228560, Aug 13, 2015

Filed:

Apr 27, 2015

Appl. No.:

14/696917

Inventors:

- Austin TX, US
Stephen R. HOOPER - Mesa AZ, US
Alan J. MAGNUS - Gilbert AZ, US
Justin E. POARCH - Gilbert AZ, US

International Classification:

H01L 23/495
H01L 23/31

Abstract:

A structure to improve saw singulation quality and wettability of integrated circuit packages () is assembled with lead frames () having half-etched recesses () in leads. In one embodiment, the structure is a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package () that includes a semiconductor device encapsulated in a package body () having a plurality of leads (). Each lead has an exposed portion external to the package. There is recess () at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material ().