Kai Feng Cheng

US Patent:

6810467, Oct 26, 2004

Filed:

Aug 21, 2000

Appl. No.:

09/643382

Inventors:

Manoj Khare - Saratoga CA
Faye A. Briggs - Portland OR
Kai Cheng - Portland OR
Lily Pao Looi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711146, 711144, 711145, 711140

Abstract:

An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the systems nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.

US Patent:

7234029, Jun 19, 2007

Filed:

Dec 28, 2000

Appl. No.:

09/749660

Inventors:

Manoj Khare - Saratoga CA, US
Faye A. Briggs - Portland OR, US
Akhilesh Kumar - Sunnyvale CA, US
Lily P. Looi - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08
G06F 13/00

US Classification:

711146, 711100, 711141

Abstract:

A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

US Patent:

8527836, Sep 3, 2013

Filed:

Jul 1, 2011

Appl. No.:

13/175472

Inventors:

Ramesh Subashchandrabose - Bangalore, IN
Tessil Thomas - Bangalore, IN
Sambaran Mitra - Barasat, IN
Debaleena Das - Los Gatos CA, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00
G11C 29/00
G06F 12/06

US Classification:

714758, 714753, 714756, 714767, 714768, 714769, 714773, 714784, 711 5

Abstract:

Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

US Patent:

7996625, Aug 9, 2011

Filed:

Apr 30, 2007

Appl. No.:

11/790989

Inventors:

Manoj Khare - Saratoga CA, US
Faye A. Briggs - Portland OR, US
Akhilesh Kumar - Sunnyvale CA, US
Lily P. Looi - Portland OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711146, 711100, 711141, 711154

Abstract:

A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

US Patent:

20020087766, Jul 4, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751623

Inventors:

Akhilesh Kumar - Sunnyvale CA, US
Manoj Khare - Saratoga CA, US
Lily Looi - Portland OR, US
Ling Cen - Austin TX, US
Kenneth Creta - Gig Harbor WA, US
Steve Kulick - Portland OR, US
Kai Cheng - Portland OR, US
Robert George - Austin TX, US
Sin Tan - Portland OR, US

International Classification:

G06F013/00

US Classification:

710/108000

Abstract:

In a multi-node system, a method and apparatus to implement a locked-bus transaction is described. In one embodiment, a bus agent initiates a locked-bus transaction and a node controller defers the transaction so that it will be initiated again at a later time. The node controller then sends the locked bus request to one or more other node controllers in the system, which prevent bus transaction at their respective busses. Once the requesting node controller receives confirmation that the other nodes are locked, it can allow the locked-bus transaction to proceed from the bus agent.

US Patent:

20130052131, Feb 28, 2013

Filed:

Aug 24, 2012

Appl. No.:

13/593907

Inventors:

Zhen Cheng - Mountain View CA, US
Kai Cheng - Mountain View CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

A61K 49/00
G01N 29/14
C07K 2/00
C07H 21/00
C08B 37/00
C07J 51/00
C07F 19/00
A61K 38/02
A61K 31/715
A61K 39/00
A61K 31/282
A61K 31/56
A61K 31/555
A61P 35/00
A61P 37/04
A61K 49/22
C07H 23/00
A61K 51/02
A61K 31/7135
B22F 1/00
B32B 15/02
G01N 21/65
B82Y 5/00
B82Y 15/00

US Classification:

424 161, 435 723, 435 61, 435 71, 435 29, 530300, 530400, 536 231, 536121, 552504, 556110, 544225, 424 91, 514 11, 514 54, 4241931, 514495, 514169, 514184, 514186, 424 95, 514 23, 514 44 R, 420591, 428402, 977906, 977904, 977774, 977927

Abstract:

Embodiments of the present disclosure, in one aspect, relate to a nanoparticle, methods of imaging a tumor, method of imaging a disease, method of treating a condition, disease, or related biological event, or the like.

US Patent:

20130332795, Dec 12, 2013

Filed:

Aug 15, 2013

Appl. No.:

13/968266

Inventors:

Ramesh Subashchandrabose - Bangalore, IN
Tessil Thomas - Bangalore, IN
Sambaran Mitra - Barasat, IN
Debaleena Das - Los Gatos CA, US
Kai Cheng - Portland OR, US

International Classification:

G06F 11/10

US Classification:

714758, 714807

Abstract:

Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

US Patent:

20190192761, Jun 27, 2019

Filed:

Nov 12, 2018

Appl. No.:

16/186947

Inventors:

- Stanford CA, US
Xuechuan HONG - Wuhan City, CN
Hongjie DAI - Cupertino CA, US
Hao CHEN - Wuhan City, CN
Alexander ANTARIS - Stanford CA, US
Kai CHENG - Mountain View CA, US

International Classification:

A61M 5/00
A61K 47/60
C09B 57/00
A61K 49/00
A61K 49/22
C07K 14/765
A61K 41/00

Abstract:

Disclosed is a small molecule dye for use in imaging in the near-infrared window, namely between 1000 nm-1700 nm wavelength. The present dyes are also useful for photoacoustic imaging and photothermal therapy. The dyes have a structure of a D-A-D (donor-acceptor-donor) fluorescent compound core and side chains rendering the compounds water soluble and easily conjugated to hydrophilic polymers and/or targeting ligands. Further disclosed is compound, CH1055 that can be PEGylated, conjugated to a targeting ligand, or conjugated to taurine. Key steps utilized to assemble the core structure of the target included a cross-Suzuki coupling reaction, iron reduction and N-thionylaniline induced ring closure. Four carboxylic acid groups were introduced into the donor-acceptor-donor (D-A-D) type fluorescent compound to impart a certain aqueous solubility and to allow facile conjugation to targeting ligands.